Forum Discussion
RiscFree debugging fails after first debug
I have a simple Nios V system that prints "Hello World" on a DE-10. The design is generated using Quartus Std Lite 23.1.1. The first time I try to debug, everything is fine. The second time I try to debug, Ashling returns and error when a try and add a break point:
"Operation Failed: Command aborted"
Looking at the GDB output I get:
Warning:
Cannot insert breakpoint 1.
Cannot access memory at address 0x6a8
The only way I can recover is to program the .sof again, but it only works for one debug.
Is there anything that I can do because its annoying to have to program the SOF every time I want to debug?
Notes:
There is something strange in the at the ash-riscv-gdb-server output. On the first (successful) run it looks like:
Ashling GDB Server for RISC-V (ash-riscv-gdb-server).
v23.4.1, 03-Nov-2023, (c)Ashling Microsystems Ltd 2023.
Initializing connection ...
Checking for an active debug connection using the selected debug probe (SN: 1):
Connected to target device with IDCODE 0x2d020dd using USB-Blaster-2 via JTAG at 16.00MHz.
Info : Active Harts Detected : 1
Info : [0] System architecture : RV32
Info : [0] Number of hardware breakpoints available : 1
Info : [0] Number of program buffers: 8
Info : [0] Number of data registers: 2
Info : [0] Memory access -> Program buffer
Info : [0] Memory access -> Abstract access memory
Info : [0] CSR & FP Register access -> Abstract commands
Waiting for debugger connection on port 3333 for core 0.
Press 'Q' to Quit.
On the second (failed) an subsequent runs it looks like:
Ashling GDB Server for RISC-V (ash-riscv-gdb-server).
v23.4.1, 03-Nov-2023, (c)Ashling Microsystems Ltd 2023.
Initializing connection ...
Checking for an active debug connection using the selected debug probe (SN: 1):
Connected to target device with IDCODE 0x2d020dd using USB-Blaster-2 via JTAG at 16.00MHz.
Info : Active Harts Detected : 1
Info : [0] System architecture : RV32
Info : [0] Number of hardware breakpoints available : 1
Info : [0] Number of program buffers: 8
Info : [0] Number of data registers: 2
Info : [0] Memory access -> System bus (Data width : 128 Address size : 57)
Info : [0] Memory access -> Program buffer
Info : [0] Memory access -> Abstract access memory
Info : [0] CSR & FP Register access -> Abstract commands
Waiting for debugger connection on port 3333 for core 0.
Press 'Q' to Quit.
It looks like it has detected Memory access -> System bus (Data width : 128 Address size : 57) as a way to access memory. This seems strange because it didn't exist on the first run. Also the values for the width + address size are just wrong (and can change between runs).
This also happens if I use ash-riscv-gdb-server from the command line outside the RiscFree IDE. I have also tried using OpenOCD. It never fails. However, it causes ash-riscv-gdb-server to fail in the same way when its executed after OpenOCD.
Externally I was also able to debug multiple times provided I don't shutdown the ash-riscv-gdb-server. Everything starts failing when ash-riscv-gdb-server is re-run.
Hi
Sorry in that cause you will need to wait for the release of Quartus Standard 24.1 in Q1 next year.
Regards
Jingyang, Teh
20 Replies
- BrendenB
New Contributor
I tried the option "Issue TAP_Reset" and still the same outcome. Works on the first connection. Wont work after until I re-program the SOF.
Is there some form of debugging that I can enable that might debug this problem?
- XleraSolutions
New Contributor
same, the Issue TAP Reset does not affect the problem.
- tehjingy_Altera
Regular Contributor
HI
After asking around, it seems like it is a tool issue and it have been fix in the latest quartus version.
Could you try migrating your design to a newer quartus version maybe 24.1pro ?
Regards
Jingyang, Teh
- BrendenB
New Contributor
I can't go to a pro version because I am using a Cyclone V and its only supported on standard/lite versions.
However, I did download the 24.2 pro version is tried the newer riscfree in that version. It produced the same results. The first debug after SOF programming works fine. The second and subsequent debug fail until the SOF is re-programmed. The attached file shows the commands I ran to test. It broke both when using riscfree UI and the command line directly.
I had to use the SOF generated on standard as pro can't generate a SOF for my Cyclone V.
At what level was the bug fixed? Was it in the IP or the software? If its in the IP, I wont be able to check because its not possible to use pro to generate a SOF for my FPGA. If its in the software, then it still seems to be happening in 24.2 pro.
- tehjingy_Altera
Regular Contributor
Hi
You will need to upgrade the whole project of the NiosV project.
Did you meet any error when upgrading the project to 24.2 pro?
It is an bug in rtl code of the NiosV core that is not compatible with tool.
Regards
Jingyang, Teh
- tehjingy_Altera
Regular Contributor
Hi
Any update on this case?
Are you able to migrate the design and test out if the problem still occur?
Regards
Jingyang, Teh
- BrendenB
New Contributor
I am using a Cyclone V FPGA which means I can't use pro as its not supported. See https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/devices-support.html#cyclone%C2%AEseries
- tehjingy_Altera
Regular Contributor
Hi
Sorry in that cause you will need to wait for the release of Quartus Standard 24.1 in Q1 next year.
Regards
Jingyang, Teh
- BrendenB
New Contributor
This was indeed fixed in Standard/Lite 24.1.
- tehjingy_Altera
Regular Contributor
Hi
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards
Jingyang, Teh