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BrendenB's avatar
BrendenB
Icon for New Contributor rankNew Contributor
2 years ago
Solved

RiscFree debugging fails after first debug

I have a simple Nios V system that prints "Hello World" on a DE-10. The design is generated using Quartus Std Lite 23.1.1. The first time I try to debug, everything is fine. The second time I try to ...
Nios Cpu
  • tehjingy_Altera's avatar
    tehjingy_Altera
    1 year ago

    Hi


    Sorry in that cause you will need to wait for the release of Quartus Standard 24.1 in Q1 next year.


    Regards

    Jingyang, Teh


BrendenB's avatar
BrendenB
Icon for New Contributor rankNew Contributor
2 years ago

I can't go to a pro version because I am using a Cyclone V and its only supported on standard/lite versions.

However, I did download the 24.2 pro version is tried the newer riscfree in that version. It produced the same results. The first debug after SOF programming works fine. The second and subsequent debug fail until the SOF is re-programmed. The attached file shows the commands I ran to test. It broke both when using riscfree UI and the command line directly.

I had to use the SOF generated on standard as pro can't generate a SOF for my Cyclone V.

At what level was the bug fixed? Was it in the IP or the software? If its in the IP, I wont be able to check because its not possible to use pro to generate a SOF for my FPGA. If its in the software, then it still seems to be happening in 24.2 pro.