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Altera_Forum
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16 years ago

Reset from Swtich Button hangs Nios II system

Dear all,

I am using Stratix III FPGA Development Kit.

1 Nios II/e processor.

1 On-chip Memory (128 Kb).

1 DDR2 SDRAM High Speed Controller for connection to on board DDR2 1Gb DIMM.

1 Jtag_Uart (to use printf)

I connected one of the user switch buttons (Pin_B17) to the reset_n signal of the system. Actually there are two reset signals:

One for CPU, On-Chip Memory, all Avalon interfaces, arbitrators, etc. and one for High Speed Controller (global_reset_n).

I made a top design and connected two reset signals to make one reset_n for the overall system. I want to push S5 (Pin_B17) and reset the whole system.

I am running the simplest program. Just one Printf("Hello World"), and then program finishes. Actually both the hardware and software are quite complex (4 cores, and parallelized program running on such system). However, I made the simplest possible system to resolve the following problem:

Whenever Program (.text) is placed on On-chip memory, I can easily reset system (in Nios IDE per each push on button I can see "Hello World").

However, when I put (.text) on DDR2 and after running program I want to reset system it hangs. (nothing is displayed anymore). I have to reload the program to see the correct result again.

The problem is not related to pin assignments, adding constraints, etc., because much complex system (4 cores with shared on chip memory) is running perfectly in the first load of programs (everything .text, .rodata, .rwdata, .heap, .stack are placed on DDR2), but whenever I want to reset system it hangs.

I connected DDR2 Controller’s (global_reset_n) signal to the overall system’s reset_n, because I saw the same connection in one of the example designs (stratixiii_3sl150_dev_niosII_standard) on disk provided with the board. Even this example has the same problem with reset.

Please give me some guidance. I don’t want to reload my system each time when I need to reset it.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    This behavior is not unexpected. There are two reasons I can think of:

    1 - The DDR2 controller requires a certain amount of time to initialize the DDR2 memory. It is not expected that the SDRAM's contents remain valid during this time (because the ram is not being refreshed).

    2 - Wouldn't the calibration sequence used by the altmemphy core wipe out any data that previously existed in the first several words of the RAM (something like 32 or 64)? This would trash your code.

    What you could try doing is bringing out the user controlled refresh signal from the DDR2 core and assert that instead of the global reset. Most systems reload the RAM with code (usually with a bootloader and flash) after a reset. I assume for some good reason, yours does not.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you Jake for reply.

    2nd point "Wouldn't the calibration sequence used by the altmemphy core wipe out any data that previously existed in the first several words of the RAM (something like 32 or 64)? This would trash your code." is not a problem. I knew about this problem before, so I left quite enough address space in the beginning of DDR2.

    about user controlled refresh signal:

    do you mean "local_refresh_req" signal? I found it is always connected to logical "0". If this is the right signal, then I should instead of "reset_n" connect "~reset_n". There is also an output "local_refresh_ack" signal. Should I use that one as well? Like assert "local_refresh_req", then wait for "local_refresh_ack" and finally assert "reset_n" signal for the remaining part of the nios ii system?

    Also I found "soft_reset_n" signal? Maybe this one can be used for my problem.

    I never used DDR2, and all this is completely new for me.

    So I would appreciate any help.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Have you also tried just resetting the NIOS and leaving everything else running?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes I did, but it again does not work.

    I am reseting the rest of the system except DDR2 controller ("global_reset_n" signal is always connected to 1'b1). But again system hangs. I am sure that all the trouble comes from DDR2 controller, however it is encrypted ("auk_ddr_hp_controller.vhd") and there is no way to go into details (which actually will take a lot of time) to understand what is really happening.

    Arsen.