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Altera_Forum
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16 years ago

Reset from Swtich Button hangs Nios II system

Dear all, I am using Stratix III FPGA Development Kit. 1 Nios II/e processor. 1 On-chip Memory (128 Kb). 1 DDR2 SDRAM High Speed Controller for connection to on board DDR2 1Gb DIMM. ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thank you Jake for reply.

2nd point "Wouldn't the calibration sequence used by the altmemphy core wipe out any data that previously existed in the first several words of the RAM (something like 32 or 64)? This would trash your code." is not a problem. I knew about this problem before, so I left quite enough address space in the beginning of DDR2.

about user controlled refresh signal:

do you mean "local_refresh_req" signal? I found it is always connected to logical "0". If this is the right signal, then I should instead of "reset_n" connect "~reset_n". There is also an output "local_refresh_ack" signal. Should I use that one as well? Like assert "local_refresh_req", then wait for "local_refresh_ack" and finally assert "reset_n" signal for the remaining part of the nios ii system?

Also I found "soft_reset_n" signal? Maybe this one can be used for my problem.

I never used DDR2, and all this is completely new for me.

So I would appreciate any help.