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Altera_Forum
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16 years ago

Reset from Swtich Button hangs Nios II system

Dear all, I am using Stratix III FPGA Development Kit. 1 Nios II/e processor. 1 On-chip Memory (128 Kb). 1 DDR2 SDRAM High Speed Controller for connection to on board DDR2 1Gb DIMM. ...
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Altera_Forum
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16 years ago

This behavior is not unexpected. There are two reasons I can think of:

1 - The DDR2 controller requires a certain amount of time to initialize the DDR2 memory. It is not expected that the SDRAM's contents remain valid during this time (because the ram is not being refreshed).

2 - Wouldn't the calibration sequence used by the altmemphy core wipe out any data that previously existed in the first several words of the RAM (something like 32 or 64)? This would trash your code.

What you could try doing is bringing out the user controlled refresh signal from the DDR2 core and assert that instead of the global reset. Most systems reload the RAM with code (usually with a bootloader and flash) after a reset. I assume for some good reason, yours does not.

Jake