Altera_Forum
Honored Contributor
10 years agoReceived waveform frequency is way too low than it was sent
I am using Quartus 12.1 sp1, vhdl and Altera Nios II programmed in C code for DE0-Nano Development. Basically, what I have is, data is sent from fpga vhdl block to NIos II system, Nios II system sends the data to serial port, Matlab access the serial port to real time plot the graph.
In my system, the rate the graph is plotted is much slower (11Hz) than the rate the processor speed (50MHZ). So I do some buffering and send the data for plotting afterwards. I am buffering data received from fpga vhdl say 1000 sample points and save it in sdram... after saving these 1000 sample points, the C code will send data to uart so that Matlab can access these serial port data and plot the graph real time. Please refer to this image: http://www.alteraforum.com/forum/attachment.php?attachmentid=11015&stc=1 My problem is, a complete cycle of sinewave obtained from fpga is with a frequency of 50Hz, so it should be having a period of 0.02 seconds instead of 0.16 minutes as I got now, I don't know what could be the problem? Forgive me, I am newbie to signal processing.. Thank you.
int max_sample =1000;//number of sample points wanted
if(a_out_data==1)//check if it is the beginning of a sinusoidal waveform?
{
for(i=0;i<max_sample;i++)//start the process of buffering data
{
vref_data = IORD_ALTERA_AVALON_PIO_DATA(vref_base);//read a single value of reference voltage from fpga
*(pSDRAM+i)=vref_data;//save this single value in a location of SDRAM specified in SDRAM_U1_BASE
}
}
for(i2=0;i2<i;i2++)//start the process of sending data to uart for all data saved previously
{ data16=*(pSDRAM+i2);//access each value from SDRAM
//send data to uart before increment i++
}