Receive LVDS signals with FPGA

I’m going to Receive LVDS signals(data rates : 600Mbps) with FPGA (Cyclone V), There are 8 LVDS signals,12bit per channel from an image sensor, The sensor manual states that there is a difference in phase between these LVDS signals and that the signal should be trained before acceptance.

As shown, the training is divided into bit correction、word correction and channel correction. The sensor development board uses the xilinx FPGA, which uses iodelay, bitslip and shift_register to complete 3 corrections.

Now I’m using Intel FPGA Cyclone V 5CEFA5U19I7N where is no iodelay function, I don't know how to complete the bit alignment. I tried to use the ALTLVDS_RX core to receive 8 LVDS signals directly. As shown in the figure below, the phase difference between 'rx_in' and 'rx_inclock' can be set in the IP core. I can change this value to receive some stable LVDS data, but it cannot get 8 stable LVDS data At the same time, I know this is because there is a phase difference between the LVDS signal which is not synchronous with the DDR_clock and I did not do bit correction.

So I want to know how to use Intel's FPGA to complete the bit correction, which can align the LVDS signal with DDR_CLOCK. I hope someone with similar experience or knowledge can help me.Thank you!