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WMing
New Contributor
New ContributorReceive LVDS signals with FPGA
I’m going to Receive LVDS signals(data rates : 600Mbps) with FPGA (Cyclone V), There are 8 LVDS signals,12bit per channel from an image sensor, The sensor manual states that there is a differen...
Abe
Frequent Contributor
Frequent ContributorBitSlip is incorporated into the ALTLVDS_RX IP. If you move to the last Receiver Settings tab, you will find the bitslip setting there. Here you can select how many pulses the bitslip should be and other settings.
