Receive LVDS signals with FPGA

Hi WMing,

First of all, you could implement programmable IO delay (like Xilinx iodelay analog which you mentioned) on Cyclone V, both static from IO assignment and even dynamic, which I think you doesnt' need.

You must also write correct timing constraints for your I/O Source-Synchronous system (which your Image Sensor outputs) for PLL to properly adjust clock phase.

Best regards,

Ivan