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WMing
New Contributor
New ContributorReceive LVDS signals with FPGA
I’m going to Receive LVDS signals(data rates : 600Mbps) with FPGA (Cyclone V), There are 8 LVDS signals,12bit per channel from an image sensor, The sensor manual states that there is a differen...
IDeyn
Contributor
ContributorHi WMing,
First of all, you could implement programmable IO delay (like Xilinx iodelay analog which you mentioned) on Cyclone V, both static from IO assignment and even dynamic, which I think you doesnt' need.
You must also write correct timing constraints for your I/O Source-Synchronous system (which your Image Sensor outputs) for PLL to properly adjust clock phase.
Best regards,
Ivan
