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WMing's avatar
WMing
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7 years ago

Receive LVDS signals with FPGA

I’m going to Receive LVDS signals(data rates : 600Mbps) with FPGA (Cyclone V), There are 8 LVDS signals,12bit per channel from an image sensor, The sensor manual states that there is a differen...
WMing's avatar
WMing
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7 years ago

Thank Abe for answering​，I konw the BitSlip，it's for word correction, right? just like when the trainning word is 111111000000, and the word received is 1111100000001, then I can use the bitslip function to get 111111000000, My problem now is that my sampling clock and data are not aligned. I even can not receive the 111110000001. so I want to do the bit correction, thank you.

murillo's avatar
murillo
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5 years ago

Hi WMing,

I am also working with the same sensor and have the same problem as you. The problem is in Cyclone V you dont have a DPA right! (for the bit alignment!) Is it posible to use the ALTIOBUF and using the io_config iterface manually config the delays or maybe just using the input assignments(add_input_delay)? I wonder how you solved your problem.

On Xilinx you have the IODELAY2 and using the input CAL you will do the alignment automatically, having maybe a problem with overflows on the delay counter!!

so! hope to hear from you!!!