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Honored Contributor
Honored Contributorrebuilt u-boot does not recognize USB storage devices
Hi
I have an Altera SoCKit from Terasic. They provide a pre-built image that includes the SPL and u-boot.img (i.e. the contents of the "a2" partition). I can use it to access storage devices ("USB sticks") plugged into the USB2.0 port from the U-boot command line with the U-Boot usb command set. The U-boot version command shows:U-Boot 2013.01.01 (Aug 08 2014 - 10:46:23) arm-altera-eabi-gcc.exe (Sourcery CodeBench Lite 2013.11-67) 4.8.1 GNU ld (Sourcery CodeBench Lite 2013.11-67) 2.23.52.2013091 However, this pre-built version lacks some U-Boot commands (specifically md5sum) so I needed to rebuild it to include those. I used Yocto "poky" (1.7.3) with the meta-altera/recipes-bsp/u-boot recipes, pulling from https://github.com/altera-opensource/u-boot-socfpga, branch socfpga_v2013.01.01, and building with bitbake virtual/bootloader commands. I use the newly built u-boot.img to replace the one in the a2 partition with dd if=u-boot.img of=/dev/sdx3 bs=64k seek=4 (hence, leaving the SPL alone). The new U-Boot image starts up fine and can boot a Linux kernel from the MMC card, however, I can no longer access a USB storage device from the U-Boot command line, instead getting this message (with a USB stick plugged in): USB0: Core Release: 2.93a dwc_otg_core_host_init: Unable to clear halt on channel 1 (timeout HCCHAR 0xC0000000 @ffb40520) dwc_otg_core_host_init: Unable to clear halt on channel 2 (timeout HCCHAR 0xC0000000 @ffb40540) dwc_otg_core_host_init: Unable to clear halt on channel 3 (timeout HCCHAR 0xC0000000 @ffb40560) dwc_otg_core_host_init: Unable to clear halt on channel 4 (timeout HCCHAR 0xC0000000 @ffb40580) dwc_otg_core_host_init: Unable to clear halt on channel 5 (timeout HCCHAR 0xC0000000 @ffb405a0) dwc_otg_core_host_init: Unable to clear halt on channel 6 (timeout HCCHAR 0xC0000000 @ffb405c0) dwc_otg_core_host_init: Unable to clear halt on channel 7 (timeout HCCHAR 0xC0000000 @ffb405e0) dwc_otg_core_host_init: Unable to clear halt on channel 8 (timeout HCCHAR 0xC0000000 @ffb40600) dwc_otg_core_host_init: Unable to clear halt on channel 9 (timeout HCCHAR 0xC0000000 @ffb40620) dwc_otg_core_host_init: Unable to clear halt on channel 10 (timeout HCCHAR 0xC0000000 @ffb40640) dwc_otg_core_host_init: Unable to clear halt on channel 11 (timeout HCCHAR 0xC0000000 @ffb40660) dwc_otg_core_host_init: Unable to clear halt on channel 12 (timeout HCCHAR 0xC0000000 @ffb40680) dwc_otg_core_host_init: Unable to clear halt on channel 13 (timeout HCCHAR 0xC0000000 @ffb406a0) dwc_otg_core_host_init: Unable to clear halt on channel 14 (timeout HCCHAR 0xC0000000 @ffb406c0) dwc_otg_core_host_init: Unable to clear halt on channel 15 (timeout HCCHAR 0xC0000000 @ffb406e0) scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found Thinking that maybe the git repo was not up to date or too up to date, I also tried using the Quartus patches against the DENX release of 2013.01.01 from git://git.denx.de/u-boot.git, branch: u-boot-2013.01.y. All of the Quartus patches (there are 121 of them) applied cleanly, but the resulting u-boot.img built produced the same results as above. I double checked the USB configuration options in socfpga_common.h & socfpga_cyclone5.h. They seem correct. /* * USB */ #define CONFIG_SYS_USB_ADDRESS SOCFPGA_USB1_ADDRESS #define CONFIG_CMD_USB #define CONFIG_USB_DWC2_OTG #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX (I also tried with/without CONFIG_USB_OHCI to no avail). Can anybody shed some light on what I'm missing? I was hoping that I could replace the u-boot.img without involving the use of Quartus tools or rebuilding the SPL. Seems like I'm missing a patch that the pre-built image used but that is lacking from the git repo / Quartus patch set. Thanks in advance for any advice! --George Broz Moog Industrial Group
