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drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
9 months ago
Solved

ERROR building simple NIOSV Compact project

Hello and greetings All Quartus + NIOSV experts, or indeed anybody who can help me fix this error ! I am trying to build a System Verilog design, based on Platform Designer, which uses a NIOSV compa...
Embedded Applications Layer
Nios Architecture
Nios Cpu
  • Archer_Altera's avatar
    Archer_Altera
    9 months ago

    Hi Barry,

    Rather than Adding QSYS into project, please add QIP into the project. From 25.1std, the tool supports QIP only due to a change in Quartus compiler. 

    The tool also prompts with message below. 

     

    You may find a qip file located in the same folder of qsys system top level hdl file under project directory liking this.

    Hope this is helpful.

    Archer_Altera

drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
9 months ago

Hi Frank,

Thanks and now i can see my NIOSV compact core appears to be building ! Many thanks for your help.

Can i ask if you know:

 a) If there is a Tutorial guide /example design(s) from ALTERA for designing with and implementing the NIOSV core in an ALTERA FPGA ? I am using a MAX10 devices now but i will be using this processor with other ALTERA FPGAs in the near future.

b) Where is the location for the best documentation to which i can refer for using NIOSV cores in ALTERA FPGAs so that i can Bookmark the place ?

Thanks,

Barry