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Altera_Forum's avatar
Altera_Forum
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8 years ago

Questions about SOC FPGA Preloader and device tree

Hi

I’m working on a project using the Terasic Spider robot which uses the DE0 NANO SOC board. It is a Cyclone 5 board.

I’m building a Metal Detection application on top of the spider and I’m using the Terasic Spider reference Designs.

I added ADC IP component to the QSYS system and wire it to the HPS system then I compiled the design, copied the .rbf file to the SD card. Then I generated the header files (HPS_0.h) and replaced it with the old one in the Linux program reference design.

Thankfully, I was successful to build my application on top of the board. However, The spider movement stopped at all or sometimes behave weirdly.

from what I read online, I’m guessing that I have to recompile the preloader or the device tree.

My question is what is wrong with my development flow, and what else should I recompile? the preloader or the device tree or both?

Thanks.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi I'm trying to known the same. I think that if you change the rbf and dtb it works. Other possibility is recompile de preloader and create the u-boot.img. I'm trying to build the dtb but looks that it needs to add manually the new ips that I created. Have you got a solution?. Thanks.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Yes, i had to solve it because it was my senior project.

    The problem was when you compile the Quartus project and generate header file (HPS_0.h) i found out that it has some problems in the memory addresses of some of the components(some of the component has wider address space than the references design) therefore, instead of using the generated one, i modified the original HPS_0.h from the reference design(comes with the c++ program that you download from the website). i just copied the ADC component from the generated to the original and everything worked together just fine.

    you do not need to change the dtb. However, the rbf should be changed with the generated from the compilation.

    if you need more help contact me.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi, thanks but perhaps my problem is different. I post it here de1-soc problem with tree please help!! (https://www.alteraforum.com/forum/showthread.php?t=56009)

    --- Quote Start ---

    Yes, i had to solve it because it was my senior project.

    The problem was when you compile the Quartus project and generate header file (HPS_0.h) i found out that it has some problems in the memory addresses of some of the components(some of the component has wider address space than the references design) therefore, instead of using the generated one, i modified the original HPS_0.h from the reference design(comes with the c++ program that you download from the website). i just copied the ADC component from the generated to the original and everything worked together just fine.

    you do not need to change the dtb. However, the rbf should be changed with the generated from the compilation.

    if you need more help contact me.

    --- Quote End ---

    or maybe yo are right. I can edit dts but there are some problems with the sistema.sopcinfo so: 

    Component alt_vip_itc_0 of class alt_vip_itc is unknownComponent alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component pll_0 of class altera_pll is unknown
Component pll_6553600 of class altera_pll is unknown
Component reset_controller_0 of class altera_reset_controller is unknown
Component reset_controller_1 of class altera_reset_controller is unknown
Component video_pll_0 of class altera_up_avalon_video_pll is unknown
MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
Component alt_vip_itc_0 of class alt_vip_itc is unknown
Component pll_0 of class altera_pll is unknown
Component pll_6553600 of class altera_pll is unknown
Component reset_controller_0 of class altera_reset_controller is unknown
Component reset_controller_1 of class altera_reset_controller is unknown
Component video_pll_0 of class altera_up_avalon_video_pll is unknown
MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi OmranAbazid ,

    I am trying to program my FPGA on Cyclone V SoC from the HPS and I had problems to load it on the board. Could you kindly help me out?

    PS: I generated the .rbf of my new design with Quartus / Qsys 16.2.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Hi OmranAbazid ,

    I am trying to program my FPGA on Cyclone V SoC from the HPS and I had problems to load it on the board. Could you kindly help me out?

    PS: I generated the .rbf of my new design with Quartus / Qsys 16.2.

    --- Quote End ---

    Sure if I know the solution to your problem
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hello!

    I have 2 questions:

    how can I program the FPGA definitively given an RBF file? (I ve tried to write it to the QSPI flash at address 0x800000 , I ve sent the prelaoder, as well at adress 0x0, but nothing happened, the FPGA still configured same old,) (I followed the instruction here https://rocketboards.org/foswiki/documentation/gsrd131programmingfpga)

    Why I lost control to my board when I program my FPGA via quartus programmer?

    My board: Altera cyclone V SoC SX, with linux 3.7, ARM dual core A9

    Thanks in advance

    Sahbi
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Hello!

    I have 2 questions:

    how can I program the FPGA definitively given an RBF file? (I ve tried to write it to the QSPI flash at address 0x800000 , I ve sent the prelaoder, as well at adress 0x0, but nothing happened, the FPGA still configured same old,) (I followed the instruction here https://rocketboards.org/foswiki/documentation/gsrd131programmingfpga)

    Why I lost control to my board when I program my FPGA via quartus programmer?

    My board: Altera cyclone V SoC SX, with linux 3.7, ARM dual core A9

    Thanks in advance

    Sahbi

    --- Quote End ---

    the way I program my FPGA is by taking the memory card from the FPGA insert it into the computer, then I replace the RBF file available in the memory card. I put the sd card back into the FPGA and restart. the preloader will load the new configuration automatically.

    if you do it.

    you can also program the FPGA from inside the Linux directly ( i did not try this but according to this page you sent ) start reading from 'FPGA Configuration from Linux'

    programming the FPGA from Quartus programmer does work if you are using the reference design of your board and you did not change the memory addresses. otherwise, the Linux system will not be able to send commands to the right shared address. These addresses are mapped to hardware component connected to the FPGA part of the board.

    this is what I know, hope this helps.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    I replaced the .rbf file in my SDcard as well, but linux still boot on the old FPGA configuration (I named it as the old one). That's weired, isn't? from where did he get that?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    problem solved:

    In order to load an FPGA sof file, we need to generate an rbf file first (note this can be done from the GUI):

    quartus_cpf -c <input file>.sof <output file>.rbf

    Copy the .rbf file to the FAT partition of the SD card

    Then, from u-boot:

    set fpgaload "fatload mmc 0:1 0x2000000 fpga.rbf;fpga load 0 $""{fpgadata} $""{filesize}"

    set bootcmd "run mmcload;run fpgaload;run mmcboot"

    run bootcmd

    You may automate this by doing an:

    env save

    If there is no message your fpga should be programmed, check the config LED.

    If it fails with a -4 return code it has failed, most probably due to the data format.

    Check the MSEL switch settings and make sure they match the rbf format (up-up-down-up-up-up = uncompressed rbf)

    Enjoy!

    https://rocketboards.org/foswiki/documentation/loadingfpgafromuboot