Forum Discussion
23 Replies
- Altera_Forum
Honored Contributor
I implemented 16 Bit 128 Tap FIR Filter with two approach:
First with implementing the FIR on NIOS II core using C language (Software FIR Design). Second with implementing FIR as Hardware Accelerator on FPGA which get i/p values & coeff from NIOS II core and returns the the result to NIOS II core (Hardware FIR Design). Below are the links to project. Hope it helps. Software FIR Design: https://www.youtube.com/watch?v=sjjbu-lhzpc Hardware FIR Design: https://www.youtube.com/watch?v=-egwtmwg0ku - Altera_Forum
Honored Contributor
Hello everyone
I need to sent 5 different 16 bits data in 5 five clock cycles to my costum component. My Altera board is driven by a 50MHz oscillator (a period of 0.02 µs). so should I write IOWR_16DIRECT(BASE , OFFSET, DATA_1); usleep(0.02); IOWR_16DIRECT(BASE , OFFSET, DATA_2); usleep(0.02); . . . IOWR_16DIRECT(BASE , OFFSET, DATA_5); - Altera_Forum
Honored Contributor
--- Quote Start --- Hi, I succeeded in implementing the system on board. My custom component is a 128 tap FIR filter which is to be started by NIOS and stimuli is also provided by nios. I made the custom component in Qsys and implemented the system. Now i am able to write the c code successfully on the NIOS without any tool errors. But, i am not able to communicate properly. Below is my code: int var =1234; IOWR(20496,0,11); printf("%d\n",var); //prints 1234 var = IORD(20496,0); printf("%d\n",var); // prints 0 When I am reading the same address and offset, it gives 0. --- Quote End --- HI, I'm currently facing the issues as mentioned in the quote above. May I know the way you resolve it? Thanks HY