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Altera_Forum
Honored Contributor
12 years agoI implemented 16 Bit 128 Tap FIR Filter with two approach:
First with implementing the FIR on NIOS II core using C language (Software FIR Design). Second with implementing FIR as Hardware Accelerator on FPGA which get i/p values & coeff from NIOS II core and returns the the result to NIOS II core (Hardware FIR Design). Below are the links to project. Hope it helps. Software FIR Design: https://www.youtube.com/watch?v=sjjbu-lhzpc Hardware FIR Design: https://www.youtube.com/watch?v=-egwtmwg0ku