Problem with the new Nios II 1.1 release

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originally posted by mir@Jan 12 2005, 10:24 AM

with the new version of nios ii (1.1) a 8-bit register slave uses the same address scheme as a 32-bit register. byte accesses to offset 0, 1, 2 and 3 always result in an access to address 0. so every software address has to be multiplied by 4.

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Mike,

Thanks for sharing your explanation here. One note, though, what you're describing is the difference between an avalon "memory slave" (called dynamic bus sizing) versus "register slave" (called native addressing). In a nutshell, the CPU always "thinks" in byte addresses, so when talking to a register slave the low two address bits may be shifted right (going from the CPU to the peripheral); thus, the CPU has to go to the next "word" in memory (address+4) to get to the next peripheral register, regardless of the data width of the peripheral.

My hunch is that somewhere in the upgrade process this mode (for your peripheral) got changed. If you'd like to pursue this further we can discuss more.. on the other hand if you're content with the current behavior I'll leave it at that.

BTW -- if you are not talking to memory, but rather registers, I would reccomend keeping the avalon mode as it is now.

Here's a pretty good table showing what we mean.

http://www.altera.com/literature/manual/mn..._avalon_bus.pdf (http://www.altera.com/literature/manual/mnl_avalon_bus.pdf)

Page 100. In this case you have a 32 bit master talking to a 8 bit registered slave (native alignment).

Hello,

Here is some new information about my design. The CPLD which is connected to the external bus is using only one address. And after changing the timing of this “Interface to User Logic” in SOPC it is possible to write to a register which is implemented in the CPLD. So now this one is working. But changing the timing of the others components has no positive result. At the moment I don’t have enough time to check the things with a logic analyzer (and unfortunately I don’t have one here) but I think the above information could help in finding a solution.

Bye,

niosIIuser

Hi Jesse, hi BadOmen,

I know what you mean. But this (normal) behaviour has begun now with NIOS II 1.1. My design grew up as NIOS/Quartus grew up. So I don't know under which conditions I've created these 8-bit-interfaces. But it worked in all previous versions (NIOS 3.1 to NIOS-II 1.01) with byte offsets.

But this issue is obviously not niosIIuser's problem. I think about updating again to NIOS II V1.1.

Thanks for your help.

Mike

Hello,

Now the problem is solved. Like it was discussed several times in the forum I had to change the address when using IOWR and IORD. But this was not the only thing I had to change. The system was running with a system clock of 70 MHz. Now it is only running with 65! It’s the same design. Nothing has changed except using Nios II 1.1 and not Nios II 1.0.1.

Bye,

niosIIuser