Forum Discussion
Altera_Forum
Honored Contributor
21 years agoHello,
Here is some new information about my design. The CPLD which is connected to the external bus is using only one address. And after changing the timing of this “Interface to User Logic” in SOPC it is possible to write to a register which is implemented in the CPLD. So now this one is working. But changing the timing of the others components has no positive result. At the moment I don’t have enough time to check the things with a logic analyzer (and unfortunately I don’t have one here) but I think the above information could help in finding a solution. Bye, niosIIuser