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Altera_Forum
Honored Contributor
15 years agoProblem with Compiler Optimization
Hi,
I am designing a Hardware Accelerator for IDCT which requires 17 inputs. I am writing into the 17 registers with the last register a control register which starts the hardware accelerator FSM. Immediately I am reading the computed IDCT values from the registers. But for some reason (probably due to compiler optimization) the reads are going to the hardware accelerator first and then the writes are going. Because of this I am getting the wrong values. The compiler optimization level I am using is O0. Below is the part of code used. //Writing *(volatile int *)(IDCT_BASE + 0) = 0x17; *(volatile int *)(IDCT_BASE + 4) = 0x17; *(volatile int *)(IDCT_BASE + 8) = 0x17; *(volatile int *)(IDCT_BASE + 0xc) = 0x17; *(volatile int *)(IDCT_BASE + 0x10) = 0x17; *(volatile int *)(IDCT_BASE + 0x14) = 0x17; *(volatile int *)(IDCT_BASE + 0x18) = 0x17; *(volatile int *)(IDCT_BASE + 0x1c) = 0x17; *(volatile int *)(IDCT_BASE + 0x20) = 0x17; *(volatile int *)(IDCT_BASE + 0x24) = 0x17; *(volatile int *)(IDCT_BASE + 0x28) = 0x17; *(volatile int *)(IDCT_BASE + 0x2c) = 0x17; *(volatile int *)(IDCT_BASE + 0x30) = 0x17; *(volatile int *)(IDCT_BASE + 0x34) = 0x17; *(volatile int *)(IDCT_BASE + 0x38) = 0x17; *(volatile int *)(IDCT_BASE + 0x3c) = 0x17; *(volatile int *)(IDCT_BASE + 0x40) = 0x17; //Reading d0 = *(volatile int *)(IDCT_BASE + 0); d1 = *(volatile int *)(IDCT_BASE + 4); d2 = *(volatile int *)(IDCT_BASE + 8); d3 = *(volatile int *)(IDCT_BASE + 0xc); d4 = *(volatile int *)(IDCT_BASE + 0x10); d5 = *(volatile int *)(IDCT_BASE + 0x14); d6 = *(volatile int *)(IDCT_BASE + 0x18); d7 = *(volatile int *)(IDCT_BASE + 0x1c); The computed values are stored in the first 8 registers. When I observed it in simulation the reads are going first in burst mode following by the write to the 17th register followed by write to first 8 registers and the write to the next 8 registers. Can someone help me with this. Thanks.3 Replies
- Altera_Forum
Honored Contributor
The compiler should be generating the memory transfers in the expected order (regardless of the optimisation level).
I suspect (as is common) you've forgetten to bypass the data cache. - Altera_Forum
Honored Contributor
Hi Dsl,
Your suggestion sounds pretty relevant. Can you please explain it more? How can I bypass the data cache? - Altera_Forum
Honored Contributor
Hi Dsl,
Checked the documents on data cache. Need to use IORD and IOWR instead of direct volatile declaration. Thanks for your suggestion :)