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Altera_Forum
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15 years ago

Problem with Compiler Optimization

Hi, I am designing a Hardware Accelerator for IDCT which requires 17 inputs. I am writing into the 17 registers with the last register a control register which starts the hardware accelerator F...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The compiler should be generating the memory transfers in the expected order (regardless of the optimisation level).

I suspect (as is common) you've forgetten to bypass the data cache.