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Altera_Forum's avatar
Altera_Forum
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19 years ago

Problem in using Avalon_Tristate_slave...

Hello,

I am currently using " Altera Stratix 1S10 Development Kit".

In SOPC Builder, I wanted to connect my User Logic to Nios Processor through Avalon_Tristate_slave.

The Entity Interface in VHDL code of my User logic [Inverter]is:

entity pipeline is

Port ( clk : in std_logic;

reset : in std_logic;

cs : in std_logic; -- chipselect

wr : in std_logic; -- write

rd : in std_logic; -- read

Outen : in std_logic; -- outputenable

dio : inout std_logic_vector(31 downto 0)); -- Data Bidirectional

end pipeline;

Here, I tried to add this New Component in SOPC builder.

While editing the componet by "Component Editor" wizard, I have chosen Avalon_tristate_slave_0 in Interface-Tab.

Then in Signals Tab, Signal type option for this bidirection signal: " dio" is not indicating the type "Data". So by this, the Component is NOT Set as "OK" by Editor. So I am unable to proceed.

I have gone through the document "mnl_avalon_spec.pdf", there I found this is the minimum requirement of signals to be done, for Tristate Bus Interface.

Then What would be the problem, Can anyone help me out??

Regards,

K V Naresh

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    You don't always need the tri-state bus.

    The tri-state bus is needed mostly when you want to share pins with cfi flash or sdram.

    eg, smc91111.

    It is easier to build the component without avalon tri-state bus, and make your io port data bus tri-state with logic.

    eg, lcd or many others on DE2 board.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by hippo@Jun 6 2006, 06:45 AM

    you don't always need the tri-state bus.

    the tri-state bus is needed mostly when you want to share pins with cfi flash or sdram.

    eg, smc91111.

    it is easier to build the component without avalon tri-state bus, and make your io port data bus tri-state with logic.

    eg, lcd or many others on de2 board.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15941)

    --- quote end ---

    --- Quote End ---

    hi

    be carefull with "inout" use inside an FPGA, it&#39;s easier to use to bus one "in" and the other "out" and multiplexe them.

    for I/O pins there is no problem to use "inout", but with an internal signal ... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

    best regards
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    I read your e-mail.

    Is your user login on the fpga or on another chip?

    You cannot use tri-state bus inside the fpga.

    An outside tri-state bus won&#39;t speed up anything.

    The avalon bus is not traditional microprocessor bus. It uses slave-side arbitration. So different masters can access different slaves at the same time.

    You should re-design your arch.

    You should use dma to transfer data to/from your user logic.

    Either use the dma core or build your own.

    If is very slow to let CPU move the data.

    You should try to use dsp builder, custom instruction or other hardware approach to process your data.

    The ethernet driver is slow. you can search on the forum to find some ways to speed up.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi Hippo,

    To use this Burst mode of Transfer,

    How to connect my User Logic in Burst mode. In Component Editor, I could not find any option related to this. In Altera-Literature, that I have, I could not find it.

    Can you please help me out!!

    Regards,

    K V Naresh
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by hippo@Jun 6 2006, 06:32 PM

    is your user login on the fpga or on another chip?

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi,

    I am working on " Altera Stratix 1S10 Development Kit" alone. My entire architecture is on this board only. I am not using any other chips.

    My User Logic is in FPGA - EP1S10F780C6 only.

    Regards,

    K V Naresh
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Did you read the quartus II v6.0 handbook vol.4 avalon switch fabric ?

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi Hippo,

    I have gone through those two documents ( Avalon Interface Spec & Avalon Switch Fabric) few weeks back.

    This Avalon Interface Spec document explains about the behaviour of Burst Transfer & its timing waveforms, but the procedure to enable Burst Transfer in SOPC Builder is not given in these documents.

    I have with me Quartus-5.1 now, It supports Burst mode of communication. right?

    Regards,

    K V Naresh
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    You should update to v6.0 .

    The component editor is for simple component. It is not possible to handle all complex construct. (or too costly to develope the software)

    You have to do it with an text editor.

    For your project, using CPU to access a burst slave won&#39;t get any gain in speed.

    You must use DMA , either the standard avalon DMA or costom designed DMA.