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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem booting program from EPCS flash and running from SRAM

Hardware and software tools:

NIOS II IDE 10.1 ("Legacy")

Quartus II 10.1

Device:Arria II GX - EP2AGX260FF35I5N

I am using software tools and hardware as described and a custom board.The problem as described in the title keeps popping up frequently in this forum so it might be a good idea to post the solution (step by step) in "Sticky" messages.Anyhow,i am facing the following problem - I have the FPGA and software tools and i also possess EPCS128 flash and 8 MB SRAM.I want to boot the Nios II program from EPCS and run in 8 MB SRAM.At this point i am able to run the program only in debug mode.In order to solve the issue I have tried the following solutions:

http://alteraforums.net/forum/showthread.php?t=20623 --->I have reached the point when i created the joint (concatinated) hw+sw bin file and i have no idea what to do next (I saw that this is impossible to burn that file to flash using the console programmer ,maybe some conversion is required?)

http://www.altera.com/support/kdb/solutions/rd12092009_471.html -->Trying to create .jic file and then burn that file using Quartus programmer.I have succeeded in doing this ,but the program still won't run after power-off and power-on,meaning it has not been programmed properly.Maybe the problem lies in the fact that the *.elf file used was from "Debug" directory and not "Release" (For some reason,the option of 'Release' has disappeared from IDE and i am not able to find that option anywhere).

Any help would be appresciated

Thank You very much,

Michael

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Check your connections to the SRAM address pins. Have a look at the board schematics and verify that they are connected at the same FPGA pins that you have declared in the Quartus project.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    the connections are fine.The memory just goes from 0x0 and 0x7ffff.After setting THOSE boundaries ,memory test goes ok,though sopc builder address range is between 0x0 and 0xfffff.Nothing i can do about that ,because that seems to be default.I use Cypress-like SRAM (ISSTIS61VPS51236A 512x36)- It has same pinout as of cypress.I have noticed this problem keeps popping up over and over again along the years(i ran into posts dating back to 2005)

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    you should edit your component so that it has the correct span. If you don't you risk having some parts of your application mapped to non existing parts of memory.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I have edited it as much as i can :). I have set memory size to the minimum-which is 1 MB.Deeper editing than that requires editing SOPC generated files - i am not sure i need to do that.I am using standard memory,512Kx36.I am sure this address span is not an issue.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Oh I didn't see the memory size... The span for a 2Mb memory is 0-0x1fffff, so you definitely have a problem with your address lines if the memory test software finds a problem at 0x80000. Be especially careful with the lew bits of the address bus. A0 from the chip point of view is in fact A2 as seen by SOPC builder on a tristate bus.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Did that change beforehand,that didn't help either.Maybe I should put 'v' on shared signals in avalon tri-state-when i put v on everything,ram didn't work at all

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Maybe got to the root of the problem.This post:

    http://www.alteraforum.com/forum/showthread.php?t=21763

    shads a light on the problem.Probable cause of the problem being that the boot loader code adapted to 8-bit external RAM.I,on the other hand possess "modern" RAM of 32-bit.So the boot loader needs to be adapted.Any chance for anybody to have the "adapted" code,or link to some official adapt by altera?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Got this problem resolved on my own,NOT thanks to any altera technical support (FAE/mySupport).After examining the schematics connection in Nios development board of the same Cypress type memory,i got suspicious.I could see that the connection isn't straightforward,i.e. address to address.After examining avalon bridge documentation:http://www.altera.com/literature/manual/mnl_avalon_spec.pdf i could see that for external device of 32-bit data width there is a different scheme of connection.The only thing that kept me from reaching the solution earlier is that i didn't connect ALL the pins and haven't set the memory size (2 MB) in SOPC properly.I should have probably got that from failing memory test at 0x80000.Anyhow it works now,and one important thing i have learned from this is to look closer at examples ,either from SOPC and also the schematics of evalution boards with similar hardware configuration.

    Good day all,

    Michael