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Altera_Forum
Honored Contributor
16 years agoProblem about C code loading to Hardwave
When I load my C code to the Hardware, I got a message
"Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloading 01000000 ( 0%) Downloading 02010020 (86%) Downloaded 55KB in 0.9s (61.1KB/s) Verifying 01000000 ( 0%) Verify failed between address 0x1000000 and 0x100BC17 Leaving target processor paused" How to solve this problem, Does anyone could help me? Does this cause any setup or coding? Thank you very much.13 Replies
- Altera_Forum
Honored Contributor
Try to run a memory test application.
What hardware are you using? - Altera_Forum
Honored Contributor
Is the memory block at 0x1000000 big enough?
It is rather a shame that error message doesn't dontain the failing address and the mis-read data. - Altera_Forum
Honored Contributor
Chip is EP2C35F672C6, Board is DE2.
Sorry, I do'nt Know How to run memory test application, Could you tell me?? --- Quote Start --- Try to run a memory test application. What hardware are you using? --- Quote End --- - Altera_Forum
Honored Contributor
When I Build the project,
the compilation tool didn't show any message about the memory. First, I only use the onchip memory, the system show the message. "ld: region onchip_mem is full (hello_world_0.elf section .text). Region needs to be 16516 bytes larger. hello_world_0 line 0 1269343999031 36 ld: section .bss [02012054 -> 0201215b] overlaps section .text [020101c8 -> 0201e083] hello_world_0 line 0 1269343999031 39 ld: section .rodata [02010020 -> 02010547] overlaps section .except but, I builded the flesh memory to cover the part. --- Quote Start --- Is the memory block at 0x1000000 big enough? It is rather a shame that error message doesn't dontain the failing address and the mis-read data. --- Quote End --- - Altera_Forum
Honored Contributor
When you create a new project, one of the templates is a memory test application. Compile it using optimizations and reduced C library so that it can fit in the on-chip RAM, run it and have it test the external RAM. It should tell you if you have a problem.
- Altera_Forum
Honored Contributor
Thank you for your help...
I found that you said.But I still don't understand. I executed the code, I got a message "Error! : Unable to load memory block at address 0x1000020 from ELF file Debug/me mtest.elf Fatal Error! : Memory map is not consistent with memory image file - check that file 'Debug/memtest.elf' is compiled and linked for system 'C:\altera\90\quartus \project_LCD_core\Block_Lcd.ptf'" I try to find the Debug/memtest.elf, but I didn't find that. Sorry, Could you help me to solve this problem. Thank you very much. --- Quote Start --- When you create a new project, one of the templates is a memory test application. Compile it using optimizations and reduced C library so that it can fit in the on-chip RAM, run it and have it test the external RAM. It should tell you if you have a problem. --- Quote End --- - Altera_Forum
Honored Contributor
--- Quote Start --- Thank you for your help... I found that you said.But I still don't understand. I executed the code, I got a message "Error! : Unable to load memory block at address 0x1000020 from ELF file Debug/me mtest.elf Fatal Error! : Memory map is not consistent with memory image file - check that file 'Debug/memtest.elf' is compiled and linked for system 'C:\altera\90\quartus \project_LCD_core\Block_Lcd.ptf'" I try to find the Debug/memtest.elf, but I didn't find that. Sorry, Could you help me to solve this problem. Thank you very much. --- Quote End --- I try to find the Debug/memtest.elf, but I didn't find that. Is it in your <Software Project Directory>/Debug/memtest.elf, but i dont think you can do any thing even if you can find it. The error above (Memory map is not consistent with memory image file) tell you that the system in your FPGA (your sof file) is not match with your memtest project. In your original error: Verify failed between address 0x1000000 and 0x100BC17 This line means that the debug monitor(Jtag debug module) was already up and running. When it try to download the machine code (your elf) into the memory located at address above, it fail to write to it. I would suggest that you:- Open up your system in Sopc Builder and check which memory located at address above, what memory are you using. (And which board your are using for this project)
- Check and make sure that the pin assignment for the memory above is correct.
- Altera_Forum
Honored Contributor
--- Quote Start --- I try to find the Debug/memtest.elf, but I didn't find that. Is it in your <Software Project Directory>/Debug/memtest.elf, but i dont think you can do any thing even if you can find it. The error above (Memory map is not consistent with memory image file) tell you that the system in your FPGA (your sof file) is not match with your memtest project. In your original error: Verify failed between address 0x1000000 and 0x100BC17 This line means that the debug monitor(Jtag debug module) was already up and running. When it try to download the machine code (your elf) into the memory located at address above, it fail to write to it. I would suggest that you:- Open up your system in Sopc Builder and check which memory located at address above, what memory are you using. (And which board your are using for this project)
- Check and make sure that the pin assignment for the memory above is correct.
- Altera_Forum
Honored Contributor
There are various way to debug this, you can use system console, mem test, or writing your own mem test.
But i think the easiest way is to look at the example design, that proven to be working. Download the ZIP file here: ftp://ftp.altera.com/up/pub/de2/de2_system_v1.2.zip The link above can be found in: http://www.altera.com/education/univ/materials/boards/unv-de2-board.html?gsa_pos=3&wt.oss_r=1&wt.oss=de2 - Altera_Forum
Honored Contributor
--- Quote Start --- There are various way to debug this, you can use system console, mem test, or writing your own mem test. But i think the easiest way is to look at the example design, that proven to be working. Download the ZIP file here: ftp://ftp.altera.com/up/pub/de2/de2_system_v1.2.zip The link above can be found in: http://www.altera.com/education/univ/materials/boards/unv-de2-board.html?gsa_pos=3&wt.oss_r=1&wt.oss=de2 --- Quote End --- Thank you for your help. I am trying...