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Altera_Forum's avatar
Altera_Forum
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20 years ago

PIO Interruptions

Hello,

I made a simple program with an ISR, and when I unmask the most periodic interruptions, they aren't seen by my program.

I have a simple question, anyone knows what is the maximum frequency to wich an irq can appear?

I mean until what frequency the NIOS can see every one of them?

Can it be changed be increasing the clock system, and in this case, what is the maximum system frequency applicable in SOPC Builder?

I hope you understood me, It's quite hard to explain it in english...

Thank you.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Nofi,

    What kind of PIO interupt r u using (level,edge and so on)?And what is connected with this PIO pin? The maximum system frequency applicable in SOPC Builder is linked with the FPGA you are using (Cyclone,Cyclone II, Stratix and so on) and the logic architecture of your system...

    But tell us more about your interupts.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    On most processors, Nios II included, the frequency at which you can see every interruptable event separately depends on many factors, including system load, which other interrupts are occurring at the same time and whether the foreground has disabled interrupts (for example because its claiming or releasing a semaphore).

    Where possible, you should design your hardware interface so it can cope if the software does not handle an interrupt before the next one occurs. In many cases you can get higher performance by deliberately merging together events and interrupting only on the last one.

    Please remember that an interrupt is just a signal to the processor that it needs to do something, not an order to carry out processing.

    Having said all that, my "rule of thumb" is that interrupts usually stay distinct below about 100us.