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Altera_Forum's avatar
Altera_Forum
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20 years ago

Pins missing in reference design?

I'm working on a design that is basically identical to the design used by the 1c20 reference card.

I'm having problems with both the CF and the Ethernet.

I guess my main problem is that their are pins assigned to every signal that goes to each of these devices. then inside the reference FPGA design not all of the pins are used. are these signals created somewhere else other than the NIOS 2 or just not needed?

for example the enet_CYCLE_n signal comes out of the EP1C20 FPGA pin B17 and heads directly to the LAN91C111 pin 35. Inside the FPGA reference design enet_CYCLE_n is not to be found.

these pins appear to be necessary for operation of the device.

Let me know what the word is on this.

thanks

Steve

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Pretty much all the Ethernet pins are routed on the PCB but not all of them are used by the lan91c111 controller in SOPC Builder. If you want to see that device working try out a hardware reference design like standard or full-featured and use the webserver software template.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    The 91c111 can operate in many different modes; see SMSC's documentation for further detail. Only one mode (32-bit asynchronous, nADS = 0) is supported in our hardware example designs.

    The other FPGA pins are un-used (tri-stated), and either left floating or pulled high/low via resistors on our dev board. The idea is to supply you with a board that can be reconfigured (by you) if you want to work with a different operating mode for that device.