Pin Assignments on the Nios II Eval Board

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originally posted by begleysm@Mar 19 2006, 05:38 PM

hi,

i ordered a nios ii eval kit from altera recently, it looks like this:

http://www.altera.com/products/devkits/images/n2eval_cyc_sml.jpg

http://www.altera.com/products/devkits/alt..._eval_1c12.html (http://www.altera.com/products/devkits/altera/kit-nios_eval_1c12.html)

i am wanting to drive an lcd using 11 of the user definable pins set to output mode. i've made a project, i have a built a system in the sopc builder based off of an altera tutorial that has a nios ii soft processor code, jtag uart, a pio core, and few other objects. in quartus ii i've got my sopc system on a block diagram with input and ouput pins attached. my problem is related to the pin assignment. i can see where i can assign pints to pin_g3, or pin_a5, etc. but, as hard as i've tried, i cant find anything, anywhere, that tells me what pin name (pin_g3, etc) is associated with which physical pin on the device (ie: the prototyping area on the right hand side of the picture).

thanks in advance,

sean

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The traditional way of doing this is to open/print out the board schematic. You should be able to trace the desired user I/O pin back to the FPGA "symbol" in the schematic and note the corresponding FPGA pin, e.g. "A5", which you&#39;d then assign in Quartus, e.g. "Pin_A5".

Quite frankly, this is an okay process if you just have a few pins, but it is error prone and I&#39;d recomend printing out the schematic and going over it with a highlighter to avoid mistakes. Troubleshooting a mis-assigned pin is no fun, so double-check as you go.

A relatively new feature in SOPC Builder gets past this - the board component/description editor, which reads a board netlist and then correlates peripheral I/O on the board with FPGA pins automatically; make the computer do the error-pront work. This is provided for most Altera dev boards, pre-configured.. but, sadly, it has not been provided for the 1C12 eval board (sorry!).

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The traditional way of doing this is to open/print out the board schematic. You should be able to trace the desired user I/O pin back to the FPGA "symbol" in the schematic and note the corresponding FPGA pin, e.g. "A5", which you&#39;d then assign in Quartus, e.g. "Pin_A5".

Quite frankly, this is an okay process if you just have a few pins, but it is error prone and I&#39;d recomend printing out the schematic and going over it with a highlighter to avoid mistakes. Troubleshooting a mis-assigned pin is no fun, so double-check as you go.

A relatively new feature in SOPC Builder gets past this - the board component/description editor, which reads a board netlist and then correlates peripheral I/O on the board with FPGA pins automatically; make the computer do the error-pront work. This is provided for most Altera dev boards, pre-configured.. but, sadly, it has not been provided for the 1C12 eval board (sorry!).

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I have the same eval board, but can&#39;t find the schematic on either one of the 2 cd&#39;s they set me with the board. Do you have any idea where I can get the schematic..

Sean,

perhaps it helps when you import the pin assignments from the original development board design. In e.g. <NIOSDIR>\examples\verilog\niosII_cyclone_1c20\full_featured\ you&#39;ll find a .qsf file which contains all the pin assignments as &#39;set_location_assignment PIN_XX ...&#39;. You can copy these lines into your own .qsf file and then label your pins to PROTO1_IO[] or PROTO2_IO[]