Honored Contributor
Honored Contributor[
The traditional way of doing this is to open/print out the board schematic. You should be able to trace the desired user I/O pin back to the FPGA "symbol" in the schematic and note the corresponding FPGA pin, e.g. "A5", which you'd then assign in Quartus, e.g. "Pin_A5". Quite frankly, this is an okay process if you just have a few pins, but it is error prone and I'd recomend printing out the schematic and going over it with a highlighter to avoid mistakes. Troubleshooting a mis-assigned pin is no fun, so double-check as you go. A relatively new feature in SOPC Builder gets past this - the board component/description editor, which reads a board netlist and then correlates peripheral I/O on the board with FPGA pins automatically; make the computer do the error-pront work. This is provided for most Altera dev boards, pre-configured.. but, sadly, it has not been provided for the 1C12 eval board (sorry!). <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13696)</div> --- Quote End --- I have the same eval board, but can't find the schematic on either one of the 2 cd's they set me with the board. Do you have any idea where I can get the schematic..
