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Altera_Forum's avatar
Altera_Forum
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20 years ago

Performance of NIOS II is 15.5 DMIPS...

Hi All,

I just ran the Dhrystone program on a "standard" design of a 1S10ES eval. board running at 50Mhz.

I get a performance of 15.5 DMIPS. This is without any changes to the default synth. settings, etc.

Has anyone tried to run it at a)Higher freq. b)Different synth. settings in order to get better performance?

What should the freq. of the "e" output from the SDRAM_PLL be set to? Thanks.http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi affluent007,

    I&#39;ve a Stratix development board 1S10 and i&#39;ve increased the processor clock till 100 MHz. I&#39;ve set the "e" output to the SDRAM at 100 MHz too, mantaining the same phase shift in ns (for my board is 3.5 ns).

    It works.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by soin@Apr 19 2005, 10:33 AM

    hi affluent007,

    i&#39;ve a stratix development board 1s10 and i&#39;ve increased the processor clock till 100 mhz. i&#39;ve set the "e" output to the sdram at 100 mhz too, mantaining the same phase shift in ns (for my board is 3.5 ns).

    it works.

    --- Quote End ---

    Hi Soin,

    I tried it as you said but I&#39;m getting timing violations.

    The best I can get is: 91.96 mhz ( period = 10.874 ns )

    What setting are you using to get 100Mhz? I tried the settings suggested:

    - Perform physical synthesis for combinational logic

    - Perform register duplication

    - Perform register retiming

    I set the optimization to "Speed" with no help.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Affluent,

    Can you describe any changes you have made in SOPC Builder? Your d-mip number sounds quite low given you&#39;re running at 50MHz. Increasing the clock speed will only increase the D-MIP result by the multiple of the clock speed increase; to improve performance I&#39;d suggest addessing whatever is wrong before trying to get the last 2-3MHz in f-max out of it.

    The D-MIPS numbers in the Nios II CPU wizard should give a clue as to what is to be expected. Is there anything different in your system? Is some other master accessing the same memory as your dhrystone app when you run it? Have you turned off the HW multiplier?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by jesse@Apr 19 2005, 02:34 PM

    affluent,

    can you describe any changes you have made in sopc builder? your d-mip number sounds quite low given you&#39;re running at 50mhz. increasing the clock speed will only increase the d-mip result by the multiple of the clock speed increase; to improve performance i&#39;d suggest addessing whatever is wrong before trying to get the last 2-3mhz in f-max out of it.

    the d-mips numbers in the nios ii cpu wizard should give a clue as to what is to be expected. is there anything different in your system? is some other master accessing the same memory as your dhrystone app when you run it? have you turned off the hw multiplier?

    --- Quote End ---

    Jesse,

    I just compiled the original "standard" 1s10es example at 80Mhz, no changes other than making the sdram_pll run at 80Mhz and got the following results:

    Register option selected? NO

    Microseconds for one run through Dhrystone: 19.0

    Dhrystones per Second: 52688.0

    VAX MIPS rating = 29.988

    I would like to make it run, though, at 100Mhz. It just can&#39;t close timing.

    Any ideas ?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi affluent007,

    I get critical timing warning too, and i&#39;m still trying to solve them. However i get this warning in paths that don&#39;t need 100 MHz timing to operate. So my system works also with this warning.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    If you want higher performance, I suggest you try using the Nios II/f instead of the Nios II/s core.

    It runs at a higher frequency than the Nios II/s so you might be able to make timing.

    It also takes fewer cycles to execute instructions so offers higher performance.

    In our current Nios II 1.1 release, the data cache is manditory in the Nios II/f although you can make it as

    small as 512 bytes to minimize resource usage. In our upcoming Nios II 5.0 release, the

    data cache will be optional (you can specify a size of 0 bytes).
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    affluent007, what is your end system going to do (not the standard design)? Although DMIPs values are an industry standard, seeing a low value isn&#39;t the end of the world (when you have a softcore processor embedded in an FPGA, there is a lot you can do to gain performance by adding additional hardware). Like James said, moving up to the f core will improve the timing and the DMIPs/MHz ratio (just take the standard design, open it in SOPC Builder, double click the Nios processor and switch it to the &#39;f&#39; core). There are many things that impact the DMIPs rating (the core type, cache, memory type, etc...).

    Also so that you know, in the same folder as the standard design is another design called "fast", you may want to give that one a try (it has onchip memory, i&d cache, f core (with level 1 debug), timer, and a JTAG uart).
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    We are wrapping up Nios II 5.0 right now so it should be available to customers in a few weeks.