Performance of NIOS II is 15.5 DMIPS...

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originally posted by soin@Apr 19 2005, 10:33 AM

hi affluent007,

i've a stratix development board 1s10 and i've increased the processor clock till 100 mhz. i've set the "e" output to the sdram at 100 mhz too, mantaining the same phase shift in ns (for my board is 3.5 ns).

it works.

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Hi Soin,

I tried it as you said but I'm getting timing violations.

The best I can get is: 91.96 mhz ( period = 10.874 ns )

What setting are you using to get 100Mhz? I tried the settings suggested:

- Perform physical synthesis for combinational logic

- Perform register duplication

- Perform register retiming

I set the optimization to "Speed" with no help.

Thanks.