Hi All, Does anyone know where I can get PCIe Enumeration program (written in 'C') to run on NIOS II ? I have the Stratix IV dev. board, configured as RooPort, plugged into a chassis with a number of other PCIe boards with a PLX PCIe switch. So, before I can transfer any data I need to run enumeration. Thanks, Shvitzer

Are you sure your setup will work? The Stratix IV Development board does not generate a 100MHz PCI output clock via its edge connector. Can you create a PCIe RootPort without a 100MHz source? Or have you hacked the board to support it? --- Quote Start --- I have the Stratix IV dev. board, configured as RooPort, plugged into a chassis with a number of other PCIe boards with a PLX PCIe switch --- Quote End --- Are you sure the slot you have plugged the PCIe board into can be operated as a RootPort. I suspect its really just a slave port. U-Boot will have PCI enumeration source. Try building U-Boot for NIOS II. Linux also has enumeration support, so you could try NIOS II uCLinux or Linux. Cheers, Dave

The 100Mhz is only on the NIOS II Avalon bus, the PCIe Avalon-MM- FIFOs have 100Mhz on one side and 50Mhz on the PCIe side. I can send config. packets to the PCIe IP and it responds correctly. Can you tell me more about "building UBoot for NIOS II" ? (I am a HW guy...) We don't intend to use Linux for now. Thanks, Shvitzer

--- Quote Start --- The 100Mhz is only on the NIOS II Avalon bus, the PCIe Avalon-MM- FIFOs have 100Mhz on one side and 50Mhz on the PCIe side. --- Quote End --- You state that you've created a PCIe "root complex" device. However, I believe this only makes sense if you are in the "system" slot of the bus. If you are in a peripheral slot, you would configure the PCIe as an "end-point". An end-point can still enumerate the PCIe bus, but it has a 100MHz input clock as a reference. --- Quote Start --- I can send config. packets to the PCIe IP and it responds correctly. --- Quote End --- Sending from what? Your NIOS processing inside the FPGA, or another peripheral in your motherboard? --- Quote Start --- Can you tell me more about "building UBoot for NIOS II" ? (I am a HW guy...) We don't intend to use Linux for now. --- Quote End --- Sorry, I haven't used it. Create a new thread with a new title and someone else can probably help. Cheers, Dave

OK, my design has a NIOS II based SOC and a PCIe Altera IP in the top-level. The NIOS II and all peripherals run on 100Mhz but interface via MM-FIFOs at 50Mhz to the PCIe IP. I have a simple utility programs that sends config. packets to the PCIe IP and it replies correctly with device ID, etc. The card is plugged in a system slot on the bus AND it provides the PCIe clock to the bus. I took over the design from someone else... so I am not sure really what differentiate a RootPort from an EndPoint other than who provides the 100Mhz clock. I did not know that an EndPoint can do enumeration. Thanks, Shvitzer

--- Quote Start --- OK, my design has a NIOS II based SOC and a PCIe Altera IP in the top-level. The NIOS II and all peripherals run on 100Mhz but interface via MM-FIFOs at 50Mhz to the PCIe IP. I have a simple utility programs that sends config. packets to the PCIe IP and it replies correctly with device ID, etc. The card is plugged in a system slot on the bus AND it provides the PCIe clock to the bus. I took over the design from someone else... so I am not sure really what differentiate a RootPort from an EndPoint other than who provides the 100Mhz clock. I did not know that an EndPoint can do enumeration. --- Quote End --- You took over the design from someone else, so first you need to understand it. If you can answer my questions, then you'll be a little further along in understanding the design you have inherited. Can you post a link to the motherboard or backplane that you are plugging the board into. As I commented above, the Stratix IV Development Board is a PCIe peripheral board, so it only makes sense that it gets configured as a PCIe end-point. When your test system powers on, the root-complex (typically a PC) writes to configuration space to tell each of the PCIe-to-PCIe bridges what their address ranges are, and writes to PCIe peripherals to tell them what their PCIe addresses are. If your root-complex (host) was running Linux, you could type lspci and see the addresses that the BIOS assigned to the PCIe bridges and peripheral boards. You comment that --- Quote Start --- I have a simple utility programs that sends config. packets to the PCIe IP and it replies correctly with device ID, etc. --- Quote End --- Where is this program running? On a NIOS II processor inside an FPGA on the Stratix IV kit, or on the host PC? Cheers, Dave

PCIe "Enumeration" SW on NIOS II ? | Altera Community

12 Replies

Altera_Forum
Honored Contributor
12 years ago
Thank you for the reply and the suggested book.
Is your hw design based on the Altera Wiki "Modular PCIe SOPC Builder Bridge Example"?
I would have asked with a PM but it's not yet permitted.

Thanks,
Michele.
Altera_Forum
Honored Contributor
12 years ago
I actually inherited a PCIe design based on a MegaWizard generated PCIe core, to which I added the NIOS II. As you may know, there are two ways to generate the PCIe system i.e. one with QSYS as in AN431 or using the Megawizard, it depends
on your application. I now have a RootPort and an EndPoint design based on the MegaWizard way. The QSYS way is somewhat simpler to design but it has a DMA for the EndPoint which I did not want.
I am not familiar with the Wiki version, it also depends on the board that you are targeting the design for. I would start by searching for PCIe reference designed for your choice of dev. board.

Cheers,
Shvitzer

Forum Discussion

PCIe "Enumeration" SW on NIOS II ?

12 Replies

Recent Discussions

NiosV µC/OS-II

Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)

AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"

Nios-V on Cyclone IV

Debug Know-How: Ashling* RiscFree* NIOS® V debug using Command Line