PCIe "Enumeration" SW on NIOS II ?

I actually inherited a PCIe design based on a MegaWizard generated PCIe core, to which I added the NIOS II. As you may know, there are two ways to generate the PCIe system i.e. one with QSYS as in AN431 or using the Megawizard, it depends

on your application. I now have a RootPort and an EndPoint design based on the MegaWizard way. The QSYS way is somewhat simpler to design but it has a DMA for the EndPoint which I did not want.

I am not familiar with the Wiki version, it also depends on the board that you are targeting the design for. I would start by searching for PCIe reference designed for your choice of dev. board.

Cheers,

Shvitzer