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Altera_Forum
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14 years ago

pausing target processor: not responding

hi all,

i hav build a system in sopc builder using nios ii cpu, jtag_uart, esps_flash_controller, ddr_high_performance_memory_controller, tse_mac, sgdma_rx, sgdma_tx, flash_tristate_bridge, ext_flash, and an onchip_memory. i managed to compile it successfully.

i downloaded the hardware image into fpga and now am trying to run a simple hello_word program on nios ii processor. but it is not happening.

the following message is being displayed in the console. . .

using cable "USB-blaster [USB-0]", device 1, instance 0x00

pausing target processor: not responding

presetting and trying again : FAILED

leaving target processor paused

if anybody knows why this is happening pls help me. . .

thank you. . .

19 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Search the forum. This is a faq.

    Common problems:

    - are you using unlicensed cores in OpenCore mode? Then you should not close the USB-Blaster message upon fpga configuration

    - check if your Quartus design meets all timings
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Or it is not coming out of reset. Make sure you have all clocks present and your reset sequence is correct.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thanks for your reply. . .

    to cris,

    am using quartus ii 8.1v which i downloaded from the net and there it is mentioned that no licence required.

    before i used niosii_ethernet_standard design example there i managed to run hellow_word pgm on nios ii processor, but the problem is with the system which i have built.

    am not closing open core plus window, in my case am using an ip which will reset after an evaluation time of 4 hours so the time remaining is 4 hours.

    is this the reason which is causing that problem. . .

    thank you. . .
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Are you sure about timings?

    Which device are you using and what are clock frequencies for Nios, ddr and tse?

    Also check if all signal are assigned to the correct pins. Maybe you missed some.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hi,

    these are the timing related warnings i am getting

    warning:

    1.at least one of the filters had some problems and could not be matched.

    2.the following clock transfers have no clock uncertainity assignment

    3.critical warning: timing requirements not met.

    4.critical warning: found minimum pulse width or period violations. see report minimum width for details.

    i dont know how to overcome these.

    sorry my questions may seem silly, but i cant help this is my first experiance with altera environment.

    am using cyclone iii dev board ( ep3c25f324c6).

    my mentor said it is some interrupt related error. is that the one causing problem...?

    thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hi,

    i haven't added system id pheripheral is it anyway related to that.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    i haven't added system id pheripheral is it anyway related to that.

    --- Quote End ---

    Is this a question or your conclusion?

    The behavior you reported is not likely due to this, unless you have loaded a wrong fpga configuration and disabled sys id check.

    The critical warnings about timing are probably the real issue.

    You can try to raise the Quartus compilation effort to overcome the problem or activate timing driven synthesis, if you haven't done it already.

    What clock frequency are you using? Maybe it's too high for your EP3C25 device: with all the components you listed I'd suggest to keep it below 100MHz.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hi,

    actually it was a question..

    except memory clock frequency (125 MHz) all are below 100MHz.

    what do you mean by raising the quartus ii compilation effort. . ???

    and i have activated time quest analyzer during synthesis. how to activate timing driven synthesis. . .??

    thank u. . .
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hi cris,

    i made some changes and recompiled my project again, now there are no warninigs related to timings. but still the problem exists.

    i am not getting what should be done. if anybody knows how to overcome this problem pls help me. . .

    thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    One way to start would be to put in signaltap and look at all of your clock networks and reset trees. If one of your clocks doesn't pop up or one of your resets doesn't release, your whole system may be stuck in reset. From personal experience this is what causes my systems to not respond.

    It is also good practice to put in a sys id block. In your current case it won't matter because it never gets to the point where it checks it, but once you do get your problems figured out it will help.