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Altera_Forum
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14 years ago

Parallel Flash memory access failed

Hello,

I am designing a simple system with a 4CE40 and a Spansion flash memory (S29GL512 : 64MB in 16bits organisation). But when I make a "hello world" software, it fails at "checking" step. Here are some more details :

HARDWARE :

- I use Quartus 11.0 toolkit.

- the board is designed by me. The FPGA owns a NIOSII/e system with a tristate bridge and the CFI flash memory interface. Nothing else.

- I checked the FPGA/memory connections, power supply etc ... => all OK

- Nothing special during synthesys process, everything looks good.

SOFTWARE :

- I built a hello world project with Eclipse rev Helios Service Release 1

Build id: 20100917-0705.

- I launch my soft with NiosII shell window using this command :

bash-3.1$ nios2-download -g hello.elf && nios2-terminal

- I get this answer :

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: OK

Initializing CPU cache (if present)

OK

Downloaded 29KB in 0.4s (72.5KB/s)

Verifying 00001020 ( 0%)

Verify failed between address 0x1020 and 0x122B

Leaving target processor paused

bash-3.1$

I think that the board has no problem (I tested each electrical connection between the FPGA and the flash). I tryed the same software with internal memory and it worked. There is a problem with the flash but I don't know where (SOPC system ? Compiler options ? ...)

Please could anybody help me to anderstand ?

Cyril

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Are you finished the project and working well with the flash?

    May you post the Qsys connections design!?

    --- Quote End ---

    Hello haulisson,

    Welcome to the forum. I attached two Qsys designs for the Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK). One is with sdram and flash memory, each having its owm address and data buses. The other is with ssram and flash memory, both sharing the same address and data buses.

    The generic tristate controller component for the external Flash memory needs to be configured for the specific Flash memory device in your system. Likewise, the pin sharer component used in the latter example needs to be configured for your design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thx fheineman, I'm very grateful.

    Could you show the configuration that you used in the signal timing TAG at Generic Tri-State Controller?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I attached two Qsys designs for the Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK). One is with SDRAM and Flash memory, each having its owm address and data buses. The other is with SSRAM and Flash memory, both sharing the same address and data buses.

    --- Quote End ---

    Can u attach whole Qsys design containing SDRAM and flash?? i want to know timing properties for the SDRAM,so if it is possible for you to place your design project instead of just screenshot?

    Is it working well? Have you tested on NEEK board? If yes then please attach design for SDRAM and flash here.I think this can be very useful for others.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi everybody,

    Sorry, but my board is beeing redesigned, so I have been working on something else. It will embed 2 SDRAM and a parallel flash sharing the same address and data bus. Designing a DDRAM board was a little bit too tricky for me :oops:

    If it works, I'll post the design (in SOPC Builder).

    Cyril
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Can u attach whole Qsys design containing SDRAM and flash?? i want to know timing properties for the SDRAM,so if it is possible for you to place your design project instead of just screenshot?

    Is it working well? Have you tested on NEEK board? If yes then please attach design for SDRAM and flash here.I think this can be very useful for others.

    --- Quote End ---

    I attached a zip file containing the three Qsys files for this project. I am trying to find a way to upload the entire Quartus II project, but it is too large for this forum (57 MB). I will upload the project files to Altera Wiki and create a page there with all the details.

    Meanwhile you can open these files in Qsys to view the various connections and component configurations.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I attached the BSF file that I used for the top level of my Quartus II project. This may give you more insight as to how the SSRAM and Flash memories are connected in the system.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I attached a zip file containing the three Qsys files for this project. I am trying to find a way to upload the entire Quartus II project, but it is too large for this forum (57 M. I will upload the project files to Altera Wiki and create a page there with all the details.

    Meanwhile you can open these files in Qsys to view the various connections and component configurations.

    --- Quote End ---

    Thanks for the qsys files,but it is SSRAM+Flash,and i wanted to see sdram+flash,very simple simple qsys design as u depicted in screenshot (Nios II + sysid+sdram+flash+tristate bridge).

    I think with only these many components,design wont be too large and before making a .zip file,u can delete "db and incremental db and unnecessary files(like .rpt and .smsg)" then make a zip file and post ur project.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Thanks for the qsys files,but it is SSRAM+Flash,and i wanted to see sdram+flash,very simple simple qsys design as u depicted in screenshot (Nios II + sysid+sdram+flash+tristate bridge).

    --- Quote End ---

    Please see the attached zip file containing a reference design for Cyclone III NEEK that uses sdram + external flash memory + triple speed ethernet components. This design should work on the NEEK without modification.

    Just download the zip file and extract to your C: drive root directory. Double-click on the niosii_ethernet_standard_3c25.qpf file to launch the Quartus II design. Open the Programmer within Quartus and change the file to the niosii_ethernet_standard_3c25.sof (it may be pointing to a different directory that does not exist). Program the NEEK, then launch the Nios II SBT for Eclipse to create software.

    I suggest creating an app based on the Memory Test example software to test the Flash memory.

    If you are really bold, you can download the Simple Socket Server Design Example located at:

    http://www.altera.com/support/examples/nios2/exm-hello_world.html

    You must follow the instructions very carefully to get the SSS example to work, but with the proper finesse, it will work on the NEEK with the attached hardware design.

    Good luck, and have fun with this...