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I attached two Qsys designs for the Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK). One is with SDRAM and Flash memory, each having its owm address and data buses. The other is with SSRAM and Flash memory, both sharing the same address and data buses.
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Can u attach whole Qsys design containing SDRAM and flash?? i want to know timing properties for the SDRAM,so if it is possible for you to place your design project instead of just screenshot?
Is it working well? Have you tested on NEEK board? If yes then please attach design for SDRAM and flash here.I think this can be very useful for others.
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