Forum Discussion
7 Replies
- Altera_Forum
Honored Contributor
Thanks for the link. I was adapting an old NIOS-II 9.0 project to NIOS-II 9.1 and got this error message when generating with SOPC Builder :
  Error: i2c: More than one port in i2c:avalon_slave_0 has role chipselect The version at http://www.nioswiki.com/perihperals/opencores_i2c fixes the problem.   If you are still looking for the I2C Controller for NIOS-II 9.0 I got mine from http://www.opencores.org/projects/i2c/ - Altera_Forum
Honored Contributor
Hello,
I use the version 9.1 of quartus and the opencore I2C master (vhdl) but I have the follows error and warning : Error: i2c_master_0.interrupt_sender: associatedAddressablePoint out of range Error: i2c_master_0.interrupt_sender: Interrupt not associated with addressable connection point. Error: i2c_master_0.interrupt_receiver: associatedAddressablePoint out of range Error: i2c_master_0.interrupt_receiver: Interrupt not associated with addressable connection point. Warning: i2c_master_0.clock_sink: Signal reset appears 2 times (only once is allowed) Warning: i2c_master_0.interrupt_receiver: Interface has no signals Warning: cpu_0.data_master/i2c_master_0.avalon_slave_0: i2c_master_0.avalon_slave_0 does not have byteenables. Narrow (less than 32-bit) writes from cpu_0.data_master will result in spurious writes to i2c_master_0.avalon_slave_0 - Altera_Forum
Honored Contributor
@bmarshall, Your link seems to be dead and couldn't find the files in opencores.org. Could you please send the .zip file to me or upload it to some site and send me the link? Thank you.
--- Quote Start --- Thanks for the link. I was adapting an old NIOS-II 9.0 project to NIOS-II 9.1 and got this error message when generating with SOPC Builder :   Error: i2c: More than one port in i2c:avalon_slave_0 has role chipselect The version at fixes the problem.   If you are still looking for the I2C Controller for NIOS-II 9.0 I got mine from opencores >> projects >> i2c --- Quote End --- - Altera_Forum
Honored Contributor
hi,
I have the same problem using open core vhd i have a problem on irq signal :error: i2c_master_0.interrupt_sender: associatedaddressablepoint out of range
error: i2c_master_0.interrupt_sender: interrupt not associated with addressable connection point.
i don't find the problem.
i add the files i2c_master_bit_ctrl.vhd,i2c_master_byte_ctrl.vhd, i2c_master_top.vhd,
i modifie the signals types.
the error appear
thanks for your help
- Altera_Forum
Honored Contributor
--- Quote Start --- @bmarshall, Your link seems to be dead and couldn't find the files in opencores.org. Could you please send the .zip file to me or upload it to some site and send me the link? Thank you. --- Quote End --- If you had searched the opencores website you would have found the file at http://opencores.org/project,i2c - Altera_Forum
Honored Contributor
I already have the file from your opencores link. That's not what I am looking for. It contains the Verilog files, yes. But, what I would like to have is the zip file same as the one you took from the NIOSwiki link I provided, with the 'HAL' and 'inc' folders and also SOPC_builder-ready .tcl file. The whole package as in the NIOSwiki website. Please provide that if you have in your project. Please zip the 'opencores_i2c' folder and send me. Thank you.
--- Quote Start --- If you had searched the opencores website you would have found the file at opencores > project,i2c --- Quote End --- - Altera_Forum
Honored Contributor
@bmarshall, thanks for your message. I couldn't send a PM due to lesser posts than required. Please send the zip file to mahendran_c_2000ATyahooDOTcom. Thanks a lot.
--- Quote Start --- If you had searched the opencores website you would have found the file at opencores > project,i2c --- Quote End ---