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Altera_Forum's avatar
Altera_Forum
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20 years ago

OpenCores 10/100 EMAC problems

Hi all,

I want to use the OpenCores 10/100 Ethernet MAC core in a NIOS I (v3.2) design on the Microtronix uKit. I use the SOPC builder version of that core what is published by MaCo Engineering (...thanks for that).

As operating system I am using the uC/OS-II together with a driver for the Ethernet MAC that I purchased some time ago from Microtronix.

In principle the system is working, but only when I configure the MAC for 10Base-T half duplex.

For some performance reasons I must operate the MAC in 100Base-T mode, but this doesn't work properly.

I observed, that all is fine for short packets. For instance ICMP request will be properly answered until the data length exceeds 300 bytes. For larger packets I can see that the system is receiving the right data and it also seems that the correct answer is put to the MAC but no packet is arriving at the other side.

So I think that the ethernet packet that the MAC sends out is somehow corrupted.

Did anybody have similar problems with the OpenCores EMAC or can somebody imagin what causes this problem?

Is there any other driver software for this MAC what I can use in conjunction with uC/OS-II?

Thanks alot in advance...

Mschulz.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi,

    I'm using the same core in some of my designs, it works flawless,

    although in a NIOS II 5.0 environment.

    I had similar problems with an other EMAC core when shifting from

    10 to 100Mbps, the problem was that the system clock was too slow.

    Whats the system clock frequency in your design?

    Does the EMAC report a TX error?

    Try if you see something with a packet sniffer like ethereal or packetyzer

    Cheers, Roger
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by rsteiner@Oct 27 2005, 12:40 PM

    hi,

    i'm using the same core in some of my designs, it works flawless,

    although in a nios ii 5.0 environment.

    i had similar problems with an other emac core when shifting from

    10 to 100mbps, the problem was that the system clock was too slow.

    whats the system clock frequency in your design?

    does the emac report a tx error?

    try if you see something with a packet sniffer like ethereal or packetyzer

    cheers, roger

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10637)

    --- quote end ---

    --- Quote End ---

    Hi Roger,

    thank you for your reply.

    My system clock is actually 66MHz but I tried it also with 75MHz.

    I already sniffed the network traffic with ETHEREAL and I figured out, that the packets sent from the embedded system are really lost ( I do see nothing in ETHEREAL).

    I will try to figure something out about TX Errors.

    What driver did you use in your design?

    Best regards, Marco.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    ...it&#39;s me again.

    I figured out, that if a packet is lost the MAC reports a TX ERROR.

    I also increased the clock rate from 66MHz to 75MHz and the point where it becomes worse shifts from 300Btyes to 1100Bytes in ICMP packet length.

    So I agree that it could be a problem of a to slow running system clock.

    I will try to setup the system clock to 100MHz - maybe this will solve to problem.

    regards, Marco.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi Marco,

    --- Quote Start ---

    originally posted by mschulz@Oct 28 2005, 12:29 AM

    my system clock is actually 66mhz but i tried it also with 75mhz.

    i already sniffed the network traffic with ethereal and i figured out, that the packets sent from the embedded system are really lost ( i do see nothing in ethereal).

    i will try to figure something out about tx errors.

    what driver did you use in your design?

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10648)

    --- quote end ---

    --- Quote End ---

    The OpenCores EMAC is running fine with 75MHz in my current design,

    although i don&#39;t know if there is a requirement for a minimum system

    clock frequency and what that would be.

    Since the EMAC is fetching the data trough its own DMA, could it be that your

    avalon bus is congested? Maybe it helps to fiddle with the arbitration.

    In my system i use a NIOS II/f core, so the caches might help.

    As for the driver, i rolled my own, i took the core&#39;s manual and the igor.c

    as documentation.

    Cheers, Roger