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Altera_Forum
Honored Contributor
21 years agoNios2 SDRAM+LAN bus sharing
Hi all!
I have been attempting to use the bus-sharing feature of the SDRAM controller, along with the LAN controller. The SDRAM seems to be working okay!, but so far no luck with the LAN controller.... Can I ask some of you folks to verify that I have carried out the address bus part-select correctly on my schematic? http://tinyurl.com/6goor (http://tinyurl.com/6goor) It took me a while to work out how exactly to do this, but I'm assuming that I do not need the full A15..0 because the device driver does not use it all? Have I broken anything by not supported the full A15..0 address bus? Thanks! ;O)3 Replies
- Altera_Forum
Honored Contributor
Hi,
Does anybody have any experience with bus-sharing feature of the SDRAM controller? Thanks! - Altera_Forum
Honored Contributor
I've never found a complete write up about the rules for signal names.
I would recomment that you break the verticle bus that connects ext_ram_bus_address[15..0] and ext_ram_bus_address[11..0] That connection looks 'wrong' to me. Keep us posted - Altera_Forum
Honored Contributor
I agree with gmm... I would expect Quiartus to give a compilation error becaue of a mis-matched bus width; you are attempting to throw away 4 address lines but Quartus doesn't know that.
You should try this in case you're seeing such a compilation error:
the 'x' means that you don't connect the line to anything. then, to get to your pin, make a separate named bus wire like this:addr ( from SOPCB ) ---- name the bus "my_addr"----x
Then quartus knows explicity that you want to connect 11..0 on your IO to 11..0 on the bus coming from the SOPCB module.x----name this one "my_addr"--------<<--IO named "my_addr-->>