nios2-download -g zImage ERROR!!!!!

whenever you updated the kernel or romfs,

you have to run "make" and "make linux image" again.

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originally posted by hippo@Nov 9 2006, 02:43 AM

whenever you updated the kernel or romfs,

you have to run "make" and "make linux image" again.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19323)

--- quote end ---

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Hi hippo

thank very much !

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--- Quote Start ---

whenever you updated the kernel or romfs,

you have to run "make" and "make linux image" again.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19323)</div>

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Hi Hippo .

I try again "make" and "make linux image" but it still error !

!!!!!!!

--- Quote Start ---

--- Quote Start ---

--- Quote Start ---

whenever you updated the kernel or romfs,

you have to run "make" and "make linux image" again.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19323)</div>

--- Quote End ---

Hi Hippo .

I try again "make" and "make linux image" but it still error !

!!!!!!!

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19331)</div>

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Please read the wiki,

http://nioswiki.jot.com/wikihome/operating...initramfsupdate (http://nioswiki.jot.com/wikihome/operatingsystems/%c2%b5clinux/uclinuxdist/initramfsupdate)

What&#39;s your error message?

Hello:

I have the same question,how did you resolve it?Please tell me.

Hi all,

I have the as error as you. Have you figure it out how to solve it ?

My output is :

root@F15:~# altera/12.1/nios2eds/bin/nios2-terminal

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [8-1]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

Linux version 3.7.0-01377-g1061bd7-dirty (root@F15) (gcc version 4.1.2)# 30 Fri Apr 19 12:09:10 EEST 2013

bootconsole [early0] enabled

early_console initialized at 0xe8001440

On node 0 totalpages: 32768

free_area_init_node: node 0, pgdat c02faac0, node_mem_map c03108a0

DMA zone: 256 pages used for memmap

DMA zone: 0 pages reserved

DMA zone: 32512 pages, LIFO batch:7

pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768

pcpu-alloc: [0] 0

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512

Kernel command line:

PID hash table entries: 512 (order: -1, 2048 bytes)

Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)

Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)

Memory available: 126776k/3130k RAM (2387k kernel code, 743k data)

NR_IRQS:64

Calibrating delay loop... 18.94 BogoMIPS (lpj=9472)

pid_max: default: 32768 minimum: 301

Mount-cache hash table entries: 512

NET: Registered protocol family 16

bio: create slab <bio-0> at 0

Switching to clocksource timer

NET: Registered protocol family 2

TCP established hash table entries: 4096 (order: 3, 32768 bytes)

TCP bind hash table entries: 4096 (order: 2, 16384 bytes)

TCP: Hash tables configured (established 4096 bind 4096)

TCP: reno registered

UDP hash table entries: 256 (order: 0, 4096 bytes)

UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)

NET: Registered protocol family 1

RPC: Registered named UNIX socket transport module.

RPC: Registered udp transport module.

RPC: Registered tcp transport module.

RPC: Registered tcp NFSv4.1 backchannel transport module.

jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.

msgmni has been set to 247

Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)

io scheduler noop registered

io scheduler deadline registered

io scheduler cfq registered (default)

ttyAL0 at MMIO 0x8001400 (irq = 2) is a Altera UART

ttyJ0 at MMIO 0x8001440 (irq = 1) is a Altera JTAG UART

console [ttyJ0] enabled, bootconsole disabled

console [ttyJ0] enabled, bootconsole disabled

mousedev: PS/2 mouse device common for all mice

TCP: cubic registered

NET: Registered protocol family 17

List of all partitions:

No filesystem could mount root, tried:

Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

Any help is greatly appreciated.

Cem

--- Quote Start ---

If you are using the MMU and you've generated a *.dts file to be linked then I'd bet that your sopc2dts has some entries that need to be tweeked. If there are unknown entries then you need to fix those first.

--- Quote End ---

Thanks for a reply. Yes, i trying to use the MMU. So i did exactly as you said. But dont know how to fix *.dts file. Dts files is written below. Could you please check it and tell me what wrong is ?

root@F15:~/luclinux/sopc2dts# cat onur.dts

/*

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

*/

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /

Yes i did as you said. But dont know how to fix .dts file. So i put here mine. Could you check and tell me what wrong is ?

root@F15:~/luclinux/sopc2dts# cat onur.dts

/*

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

*/

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /

--- Quote Start ---

If you are using the MMU and you've generated a *.dts file to be linked then I'd bet that your sopc2dts has some entries that need to be tweeked. If there are unknown entries then you need to fix those first.

--- Quote End ---

As you said i am using MMU. But it seem no unknown entries in dts files. How to understand and fix it ? If you need anything related .qsys design, please let me know.

/*

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

*/

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /