Honored ContributorHi there
I am very new to the forum and hope anyone there could help. I have designed a SOPC component that seem to work well so far since I can read and write registers from C++(nios2) however whenever I try to change the value of my register from my verilog HDL code it does not seem to work as the value written with C++ (in nios2) keeps coming back. How do I fix that can anyone help please?
Honored Contributori am very new to the forum and hope anyone there could help.
i have designed a sopc component that seem to work well so far since i can read and write registers from c++(nios2) however whenever i try to change the value of my register from my verilog hdl code it does not seem to work as the value written with c++ (in nios2) keeps coming back. how do i fix that can anyone help please?
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19218)
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--- Quote End --- Are you seeing the first access work but all other accesses fail? Chances are you are running into a cache coherency problem. Read page 131 out of 242 of this document to find out how to bypass the cache: http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf)
Honored Contributorsearch for macros IORD ad IOWR, they should skip cache
IzIHonored Contributor--- quote start ---
<!--quotebegin-tantapion@Nov 6 2006, 07:56 AM hi there
i am very new to the forum and hope anyone there could help.
i have designed a sopc component that seem to work well so far since i can read and write registers from c++(nios2) however whenever i try to change the value of my register from my verilog hdl code it does not seem to work as the value written with c++ (in nios2) keeps coming back. how do i fix that can anyone help please?
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19218)
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--- Quote End --- Are you seeing the first access work but all other accesses fail? Chances are you are running into a cache coherency problem. Read page 131 out of 242 of this document to find out how to bypass the cache: http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf) <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19225)</div> [/b] --- Quote End --- I am currently using IORD and IOWR to write and read my registers which according to the documentation (If I am right) should help bypass the cache. By the way the verilog code that is also responsible for changing the value of my register does that automatically as soon as the computation is done. Is is possible that the verilog code does not write to my register? if so why. because currently whatever changes I make to the registers from nios2 works fine. why is is then that the chages made from the verilog code(the hardware) do not show? Please help
Honored ContributorYou should always run a simulation of your HDL code before expecting it to work connected to a processor. Simulate both the the external stimuli and Avalon bus access.
IzIHonored Contributor
izi
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19262)
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--- Quote End --- I simulated the HDL code on Model Sim and everithing works fine
Honored ContributorDid you simulate processor accesses to the peripheral? You might what to check how the register behaves when it is being updated by your hardware when there is a concurrent Avalon access.
--- Quote Start --- originally posted by tantapion+nov 7 2006, 10:20 am--><div class='quotetop'>quote (tantapion @ nov 7 2006, 10:20 am)</div>--- quote start ---
<!--quotebegin-iztok.jeras@Nov 7 2006, 08:47 AM you should always run a simulation of your hdl code before expecting it to work connected to a processor. simulate both the the external stimuli and avalon bus access.
izi
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--- Quote End --- I simulated the HDL code on Sim and everithing works fine <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19264)</div> [/b] --- Quote End ---
