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pp123's avatar
pp123
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3 months ago
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NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)

Hello, I have a problem with loading elf file. Signal dbg_reset_out (used for resetting HDL components) is inactive (low) when I'm using "niosv-download -r -g exeFile.elf" command (Q25.1 Std, v...
Nios Cpu
  • LiangYuG_Altera's avatar
    LiangYuG_Altera
    2 months ago

    Hi pp123​ 

    pp123 wrote:

    Signal dbg_reset_out (used for resetting HDL components) is inactive (low) when I'm using "niosv-download -r -g exeFile.elf" command (Q25.1 Std, v25.2.1 Ashling GDB Server, Linux OS, MAX10 device, NIOS V variant m).
    The same command for Q24.1 Std (previous version of Ashling GDB Server, the same OS and PC) works.

    For me temporary solution is using additional option -o (OpenOCD instead of Ashling® RiscFree GDB Server).

    LiangYuG_Altera wrote:

    Please continue using OpenOCD.
    We have reported this failure to Ashling for investigation. 

    Ashling have responded to us, and fix their latest Ashling GDBServer in the upcoming RiscFree IDE v26.1.1-C in Quartus Prime Pro 26.1.1. Since you are using Quartus Prime Standard, you will need to wait for the Quartus Prime Standard 26.1 for the working Ashling GDBServer.

    Regards,
    Liang Yu

LiangYuG_Altera's avatar
LiangYuG_Altera
Icon for Contributor rankContributor
2 months ago

Hi pp123​ 

LiangYuG_Altera wrote:

But maybe there is a tiny delay between "reset" & "halt" in actual system.
And that delay is more noticeable in faster system.

After some experiment, there is no "tiny delay / RUNNING state" between reset & halt.
The hypothesis above is debunked.

Here are some picture showing the difference between reset run & reset halt.

reset run (Processor enters ELF's _reset/reset vector immediately after reset, aka RUNNING state after reset)

reset halt (Processor enters park loop in dm_agent immediately after reset, aka HALTED state after reset)
FYI Info on park-loop/dm-agent

 


Unfortunately, I are unable to replicate this "double reset" issue, and require more info from your design.

  1. Can you share a picture of your system?
    (Perhaps dbg_reset_out is connected differently between your & my design)

  2. Can you setup similar SignalTap above?
    (Capture the 1st instruction with dbg_reset_out falling edge as trigger during reset halt)

Regards,
Liang Yu