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otto-Q's avatar
otto-Q
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1 month ago

Nios V/g load-writeback hazard

Summary On a NiosV/g core, a long-latency load from an on-chip memory immediately followed by a short-latency load from the core's own TCM returns the TCM load's data in both destination registers. ...
Nios Cpu
CaroG_Altera's avatar
CaroG_Altera
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1 month ago

Hi otto-Q,

Thanks for the clear write-up and for confirming you saw this on Quartus 25.3. This looks like a known Nios V/g quirk with back-to-back loads when a longer-latency AXI/data_manager access is followed right away by a DTCM load. That one was fixed in Quartus Prime Pro 26.1.

If you get a chance, it’d be great if you could try your test again on 26.1 Pro with the same Platform Designer setup, and let us know if a0 and a1 come back with the right values. No rush — whenever it’s convenient. And if it still looks off on 26.1, just tell us and we’ll dig into it with you.In the meantime, that one-instruction gap (or DTCM-first order) you already found is a solid workaround on 25.3.