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andy25's avatar
andy25
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Nios V, FIFO 8 bit width, altera_avalon_fifo_read_level

I have a project built in 22.1 Standard, that has a fifo with an 8 bit width:   I can read from my Nios V using the altera_avalon_fifo_read_level function, 1 byte at a time. Each time I call...
Nios Cpu
wwanalim_intel's avatar
wwanalim_intel
Icon for Contributor rankContributor
2 years ago

Hi,


You can create an IPS ticket and share the design project. We will continue our support in the IPS case, with that


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.