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andy25's avatar
andy25
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Nios V, FIFO 8 bit width, altera_avalon_fifo_read_level

I have a project built in 22.1 Standard, that has a fifo with an 8 bit width:   I can read from my Nios V using the altera_avalon_fifo_read_level function, 1 byte at a time. Each time I call...
Nios Cpu
wwanalim_intel's avatar
wwanalim_intel
Icon for Contributor rankContributor
2 years ago

Hi,


Is the design inspired by any online references?

Could you share a screenshot of any warnings or errors that have popped up?




  • andy25's avatar
    andy25
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Online reference? No, not really.

    Warning/errors: Sure. For version 22.1 or 23.1? I'll assume 23.1. For platform designer, quartus or gcc?

    I can also create an IPS ticket and share the entire project if that would be helpful.

    I'm using the Intel Max10 Dev Kit

    23.1 Platform Designer Generate:

    Quartus has 130 warnings, most are about alter_gio_lite.sv and DDR3 timing. (I have tried a number of different things to resolve the DDR timing and nothing works. But I get the errors on both 22 and 23 so I don't think that's the problem).

    Let me know how else I can help.

    Thanks for your time,

    -Andy

    • andy25's avatar
      andy25
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      ... which is weird, because in this version of the project I've removed my use of gpio_lite. Not sure if something else is using it though. But I'm not intentionally using it anymore.