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Altera_Forum's avatar
Altera_Forum
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10 years ago

NIOS processor integration

Hi All,

I need to operate the UART and SPI IPs in the FPGA portion of ArriaV.

Since the interface to these IPs is Avalon, I got a recommendation from Altera Support to use the NIOS processor in order to setup/operate them.

Honestly I've never worked with the NIOS processor previously...

So, I have some questions to ask... Here they are:

1) How time-consumed the task is to integrate the NIOS processor into the system (for someone who never worked with it)?

2) What language is used in order to write programs to NIOS? How is it time-consumed to write the drivers for SPI and UART? Are there some examples or probably ready-for-use templates for this purpose?

3) What tools/environment is used in order to debug the code running on NIOS?

What's the less time consumed - to write HDL code for Avalon-MM Masters in order to operate the UART and SPIs or integrate the NIOS and write the code/drivers for this purpose?

Thank you!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    some idea to share.

    1) Which is depend also on what is the total system you plan to design, which is more to FGPA design area.

    2) This is become out of FGPA related already, as become a job for firmware engineer which working in C language. Need to write some initialization code and some algorithm for your application.

    3) Usually this would be the Altera's version of eclipse IDE, this is for develop, compile, and debug, include flashing as well. The Bsp of this part after the HDL/qsys generation, i believe had covered a primitive spi core/Uart driver for normal utilization.

    Frankly speaking i've not sees a design example which is covering nios and a spi/ uart for reference..
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    UART and SPI are very simple interfaces. If you're willing to invest the time you can probably get a much more compact custom FPGA only solution, without having the overhead of the avalon-mm interface. But you wont get the support from altera you would get with their cores.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    The BSP of this part after the HDL/Qsys generation, i believe had covered a primitive SPI core/UART driver for normal utilization

    --- Quote End ---

    Does the BSP come as a part of the Altera's Eclipse IDE? Is it not the same as the Altera's EDS? Is this a separate package?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, the BSP come with the Altera's version of Nios II eclipse IDE. This eclipse is different with the hps's eclipse.