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Altera_Forum
Honored Contributor
Honored ContributorNIOS processor integration
Hi All, I need to operate the UART and SPI IPs in the FPGA portion of ArriaV. Since the interface to these IPs is Avalon, I got a recommendation from Altera Support to use the NIOS proces...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The BSP of this part after the HDL/Qsys generation, i believe had covered a primitive SPI core/UART driver for normal utilization --- Quote End --- Does the BSP come as a part of the Altera's Eclipse IDE? Is it not the same as the Altera's EDS? Is this a separate package?
