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Altera_Forum
Honored Contributor
Honored ContributorNIOS processor integration
Hi All, I need to operate the UART and SPI IPs in the FPGA portion of ArriaV. Since the interface to these IPs is Avalon, I got a recommendation from Altera Support to use the NIOS proces...
Altera_ForumHonored Contributor
Honored Contributorsome idea to share.
1) Which is depend also on what is the total system you plan to design, which is more to FGPA design area. 2) This is become out of FGPA related already, as become a job for firmware engineer which working in C language. Need to write some initialization code and some algorithm for your application. 3) Usually this would be the Altera's version of eclipse IDE, this is for develop, compile, and debug, include flashing as well. The Bsp of this part after the HDL/qsys generation, i believe had covered a primitive spi core/Uart driver for normal utilization. Frankly speaking i've not sees a design example which is covering nios and a spi/ uart for reference..
