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Altera_Forum's avatar
Altera_Forum
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8 years ago

NIOS II/f altera_avalon_i2c, possible BUG in HAL

Hi,

I need a I2C master for my NIOS II/f. I thought using the I2C master which is shipped by Altera in Quartus Prime 17.0 should serve my needs.

However I'm a bit worried about the software quality of the HAL and drivers.

While testing I recognized that switching speed of the bus is not possible. The clock setting is fixed for 100kHz, setting other values results in wrong behaviour.

altera_avalon_i2c.c:302 


ALT_AVALON_I2C_STATUS_CODE alt_avalon_i2c_master_config_speed_set(
   ...
   /* adjust h/l by predetermined amount */
   scl_hcnt = scl_lcnt + ALT_AVALON_I2C_DIFF_LCNT_HCNT;  // scl_lcnt+60, should be scl_lcnt+15 for 400kHz
   scl_lcnt = scl_lcnt - ALT_AVALON_I2C_DIFF_LCNT_HCNT;
   ...

Therefore ALT_AVALON_I2C_DIFF_LCNT_HCNT should be adapted to the speed setting.

Did I miss something? What is your experience with the NIOS II software drivers?

In addition, I could not find any proper documentation with examples. Do I really have to browse the header files to get infos about the API?

Cheers, Marc

3 Replies

  • Mosari's avatar
    Mosari
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thank You report this.

    I could SCL drive 400k.

    but Is it collect which using I2C Master API ?


    I wrote cfg speed set secont argument "400000".

    But I couldn't drive 400k.

    So Google it and got this report.

    Why Intel doen't fix it.

    Anyway. Thank you.

    • jmcguire3's avatar
      jmcguire3
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Yes, this appears to be a bug in the HAL ... still ... after at least six years. I'm running an I2C bus on an Agilex part, and we added a peripheral that could run at 400kHz; we had previously been running the I2C bus at 200kHz without issue, though the generated clock looked like crap - duty cycle was nowhere near 50%.

      In the file drivers/src/intel_avalon_i2c.h we changed:

      //#define ALT_AVALON_I2C_DIFF_LCNT_HCNT 60
      #define ALT_AVALON_I2C_DIFF_LCNT_HCNT 30

      System runs fine at 100kHz, 200kHz and 400kHz now.

      Edit:

      Had better results dropping the ALT_AVALON_I2C_DIFF_LCNT_HCNT value to 10. Low-half of the SCL clock is right around 1us; high-half is nominally 1.4us.

      Scope traces are attached. One shows the system not-running with the way-too-skinny SCL clock - ALT_AVALON_I2C_DIFF_LCNT_HCNT set to 50. The other (which works) has the parameter set to 10.

  • Mosari's avatar
    Mosari
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi jmcguire3

    Thank you for reply and post scope pic.

    After that. I always use modify altera_avalon_i2c.h.

    User need define ALT_AVALON_I2C_DIFF_LCNT_HCNT by speed for now.

    I try 50kHz. So I set DIFF_LCNT_HCNT "120"

    and using ALT_AVALON_I2C_SS_MAX_HZ = "50000".

    Work is OK.

    User need set thats manually.

    reported.