Nios II processor modes

Hi,

maybe this link will help you. It's an older thread. There it is told how to set the niosii into sleep mode.

http://www.alteraforum.com/forum/showthread.php?t=25661

regards

Philipp

It is possible to gate the input clock in user vhdl, but that is likely to cause 'clock crossing bridges' to be added all over the place.

Most of the fpga is probably doesn't need continuous clocks, but any DRAM will need clocks (and regular refresh). It is also quite likely that any DRAM will need a special initialisation sequence when the clock starts.

Hi, i have written a Nios sleep component for a battery powered design.

You must write an avalon mm slave component for SOPC builder.

If you accessing your component e.g. read or write to it,

the slave responds by asserting waitrequest, stalling the transfer.

(Nios is in sleep mode)

The component have to release the waitrequest signal by an external event. e.g. a timer overfolw.

(This will wake up the Nios)

Look into the "mnl_avalon_spec.pdf" Figure 3–3. Slave Read and Write Transfers with Waitrequest. This will help.

Thank you for your quick response...

@pillemann

I am sorry to dont metioned it.... I want to do the modes in hardware.

@dsl

I think it is not the best solution because i read old threads and it said that it is not good....for me i dont know maybe i have to try it

@nicolas

I dont have much experience in sopc but as i understand that i have to make slave register and the "waitrequest" will control the sleep and wake up operations... but i think in one point i have to control it with software or??

Actually i need to implement a block and connect it to the processor. this block will be responsible of putting the prosessor in different modes. Then the input data will come from software. Any ideas?