Honored ContributorHi everyone,
I was wondering it there is a "low-power" or "standby" mode equivalent for NIOS II cores. I need a solution to shut down a number of processors in a design if they are not being used in order to lower resource usage.
Honored ContributorSorry, no such luck.
Honored ContributorYou could lower the power consumtion by stopping the processor clock. Alternatively you could try to reduce the clock frequency, although this might have some strange effects on pheripherals that relies on a specific clock frequency.
Honored ContributorThanks for the tips. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif
Honored Contributorhttp://www.niosforum.com/forum/index.php?a...t=st&f=2&t=1848 (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1848)
This is the other thread, I suggest reading the links I provided in that thread since it will give a lot of detail on how to properly turn clocks offHonored ContributorI would like to make one cautionary comment with regards to turning clocks off: Yes, it will save power. However, there are three things you should note:
(1) If you are interfacing to external synchronous memory (SDRAM) you'll want the Altera SDRAM controller to continue to operate unless you don't care about the contents of SDRAM (refresh!). (2) If you are interfacing to external memory and some other device wishes to access that memory, be careful. If you turn "off" Nios/Avalon clocks as they are accessing that memory you won't be able to access it with some other device (bus contention, avalon arbitration, etc.). (3) If you need to use any JTAG functionality associated with Nios, there is a minimum clock frequency (4x the JTAG Tck rate I believe, which can be as high as 10MHz). This isn't a factor if your final system doesn't need live-debugging or the JTAG UART. .... so be careful if you stop that clock. A safer bet might be to slow down the clock, but you'll still need to ensure that any external memory that needs refresh is handled properly.Honored ContributorHi BadOmen,
Could you please send what's the link talking about? I think the link could not be accessed :( Thanks. CarideeHonored ContributorAlso remember that if an avalon slave has a different clock from the master (even if one is just a gated version of the other) you'll get a clock crossing bridge added - slowing down the cycles and using more fpga resource.
It might be that stalling the nios cpu in a multi-cycle custom instruction (waiting for some external signal to change) is almost as low power as you'll get. Very little logic is likely to be changing value on each clock. However I don't have any measurements.
