NIOS II 'low-power' or 'standby' modes?

Also remember that if an avalon slave has a different clock from the master (even if one is just a gated version of the other) you'll get a clock crossing bridge added - slowing down the cycles and using more fpga resource.

It might be that stalling the nios cpu in a multi-cycle custom instruction (waiting for some external signal to change) is almost as low power as you'll get. Very little logic is likely to be changing value on each clock.

However I don't have any measurements.