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Altera_Forum
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14 years ago

Nios II interface with pci-express

Hi, I need to instantiate a NIOS II in an already designed FPGA using pci express communication. On the PC side, a driver is writing/reading registers in the FPGA through mapped memory. Now, I'...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks for the info dsl.

I'm not sure I grasped everything but let's see if I got at least part of it.

The NIOS and the pci express would be linked by the avalon bus. Pci express requests could write in some registers, acting as a ring command buffer. For each writing, an interrupt could be generated on the NIOS to make it read the new data. An ACK could be written when the command has been processed somewhere in a register and the CPU could read that to know when the command has been processed. This wouldn't be the fastest approach but it could work. You brought the interrupt from the NIOS approach that looks interesting. Could the NIOS trigger an MSI interrupt through the pci ex to send back an ACK easily?

I'm really new to that world of FPGA/soft cores like the NIOS and all so my vocabuly is probably inacurate... In the mean time, I'm trying to find app notes or technical design references about pci express and nios on altera's site to get familiair with all this...